alu_32_types.vhd

DLX CPU VHDL CODE UNIVERSITY

--
-- $RCSfile: ALU_32_types.vhd,v $
-- $Revision: 1.1 $
-- $Author: petera $
-- $Date: 90/06/22 12:37:16 $
--
use work.dp32_types.all;

package ALU_32_types is
  
 -- type ALU_command is (disable, pass1, incr1, 
  	--	       add, subtract, multiply, divide,
		--       log_and, log_or, log_xor, log_mask, incr4, incr8,
		  --     add_u, subtract_u, multiply_u, divide_u, seq,
--sge, sgt, sle, sll, slt, sne, sra, srl);

constant disable : bit_5 := "00000";
constant pass1   : bit_5 := "00001";
constant incr1   : bit_5 := "00010";
constant add     : bit_5 := "00011";
constant subtract: bit_5 := "00100";
constant log_and : bit_5 := "00101";
constant log_or  : bit_5 := "00110";
constant log_xor : bit_5 := "00111";
constant log_mask: bit_5 := "01000";
constant incr4   : bit_5 := "01001";
constant incr8   : bit_5 := "01010";
constant add_u   : bit_5 := "01011";
constant subtract_u:bit_5:= "01100";
constant seq	 : bit_5 := "01101";
constant sge	:  bit_5 := "01110";
constant sgt	:  bit_5 := "01111";
constant sle	:  bit_5 := "10000";
constant sll	:  bit_5 := "10001";
constant slt    :  bit_5 := "10010";
constant sne    :  bit_5 := "10011";
constant sra    :  bit_5 := "10100";
constant srl    :  bit_5 := "10101";
constant divide_u: bit_5 := "10110";
constant multiply_u:bit_5:= "10111";
constant divide :  bit_5 := "11000";
constant multiply: bit_5 := "11001";





--constant divide:bit_4:="1110";
--constant multiply:bit_4:="1111";


end ALU_32_types;