memory.vhd

DLX CPU VHDL CODE UNIVERSITY

library IEEE;
use STD.textio.all;
use IEEE.std_logic_1164.all;
use work.dp32_types.all;




entity memory is

  generic ( size : positive:=8000; -- in words (32 bit)
            Tac_read : Time := 4 ns;
            Tac_write : Time := 5 ns;
	   -- Tpd_clk_out : Time := 1 ns;
	    load_file_name : string := "dlx.out" );

  port ( phi1, phi2 : in bit;
      	 a : in bus_bit_32 bus;
	 d : inout bus_bit_32 bus;
         read : in bit;
	 write : in bit;
	 ready : out bit );

end memory;

architecture file_loaded of memory is


begin

  mem_behavior : process 
    constant high_address : natural := size - 1;

   type memory_array is
	array (natural range 0 to high_address/4 ) of bit_32;

  variable mem : memory_array;

  procedure load is

     file binary_file : text is in load_file_name;
     variable L : line;
     variable ch : character;
     variable data,addr : bit_32;

     procedure read_2_bit_32 ( L : inout line; n1,n2: out bit_32 ) is

	variable t : natural :=0;
	variable tb : bit_vector ( 3 downto 0);
     begin
        for i in 1 to 8 loop
          ch:=L(i);
	  --****************** if you get an error in here, it means the format of dlx.out is wrong. file cannot have trailing linefeeds and must have code or comments on EVERY line. comments must start at begining of the line
	  if '0' <= ch and ch <= '9' then
            t :=  character'pos(ch) - character'pos('0');
          elsif 'A' <= ch and ch <= 'F' then
            t :=  character'pos(ch) - character'pos('A') + 10;
          elsif 'a' <= ch and ch <= 'f' then
            t := character'pos(ch) - character'pos('a') + 10;
          end if;
	  natural_to_bits(t,tb);
	  n1 ( (-i+9)*4-1 downto (-i+8)*4 ) := tb;
        end loop;

	
	for i in 10 to 17 loop
          ch:=L(i);
          if '0' <= ch and ch <= '9' then
            t  := character'pos(ch) - character'pos('0');
          elsif 'A' <= ch and ch <= 'F' then
            t :=  character'pos(ch) - character'pos('A') + 10;
          elsif 'a' <= ch and ch <= 'f' then
            t := character'pos(ch) - character'pos('a') + 10;
          end if;
	  natural_to_bits(t,tb);
	  n2 ( (-i+18)*4-1 downto (-i+17)*4 ) := tb;
        end loop;

	end read_2_bit_32;


    begin
      while not endfile(binary_file) loop
        readline(binary_file, L);
        --line_number := line_number + 1;
        read_2_bit_32(L, addr,data);
--       	    ASSERT false REPORT vector_to_string(addr) SEVERITY warning;
  --     	    ASSERT false REPORT vector_to_string(data) SEVERITY warning;
        mem(bits_to_natural(addr) /4) := data;
      end loop;
    end load;

    procedure do_write is
      --subtype ls_2_bits is bit_vector(1 downto 0);
    begin

    mem(bits_to_natural(a)/4):=d;
    wait for Tac_write;
    end do_write;

    procedure do_read is
    begin
      --*********errors near here are normally caused by trying to access higher up memory then is defined. ie, acces above 2 k in a 2k defined ram.
      d <=  mem(bits_to_natural(a)/4) after Tac_read;
    end do_read;


  variable bit_temp : bit;
  begin
    load;  -- read binary memory image into memory array
    -- initialize outputs
    --d <= disabled_dlx_word;
    --ready <= '0';

    -- process memory cycles
    loop

	
	--wait on until rising_edge(phi2) and (read = '1' or write ='1');
	wait until (read = '1' or write ='1');
	
	if(read='1' and  write='0') then
	   do_read;
	end if;
	if(read='0' and write='1') then
	   do_write;
	end if;
	ready <='1';
	--wait until falling_edge(bit_to_std_logic(phi2));
	wait until (phi1='0' and phi2='0');
	wait for 10 ns;
	d<=X"0000_0000";
	
         ready <='0';
    end loop;
     
  end process mem_behavior;

end file_loaded;