links.vhd

DLX CPU VHDL CODE UNIVERSITY

library IEEE;
use STD.textio.all;
use IEEE.std_logic_1164.all;
use work.dp32_types.all;

 


 entity L64to32 is
    port(a :in bit_64;
         r1 :out bit_32;
	 y2 : out bit_32);
end L64to32;
architecture structure of L64to32 is
	alias h: bit_32 is a(63 downto 32);
	alias l: bit_32 is a(31 downto 0);
begin
	r1<=h;
	y2<=l;
end;