bidir_32.vhd

DLX CPU VHDL CODE UNIVERSITY

--
-- $RCSfile: bidir_32.vhd,v $
-- $Revision: 1.1 $
-- $Author: petera $
-- $Date: 90/05/17 16:35:52 $
--

use work.dp32_types.all;

entity bidir_32 is
  generic (Tpd : Time := unit_delay);
  port (a : inout bus_bit_32 bus;
      	b : inout bus_bit_32 bus;
	a_to_b, en : bit);
end bidir_32;

architecture behaviour of bidir_32 is

begin

  a_driver: process (en, a_to_b, b)
  begin
    if en = '1' and a_to_b = '0' then
      a <= b after Tpd;
    else
      a <= null after Tpd;
    end if;
  end process a_driver;

  b_driver: process (en, a_to_b, a)
  begin
    if en = '1' and a_to_b = '1' then
      b <= a after Tpd;
    else
      b <= null after Tpd;
    end if;
  end process b_driver;
  
end behaviour;