flags_replace.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;


entity flags_replace is
    port (fsr_in : in bit_32;
	  fsr_out : out bit_32;
	  flags : in bit_5);
end flags_replace;


architecture behaviour of flags_replace is
begin

main: process (fsr_in, flags)

begin
fsr_out<=fsr_in;
fsr_out(4 downto 0)<=flags;
fsr_out(9 downto 5)<=flags or fsr_in(9 downto 5);
fsr_out(0)<='0';

end process;





end behaviour;