leftshift.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;

entity leftshift is
    generic(width : positive);
    port(d : in bit_vector(width-1 downto 0);
         y : out bit_vector(width-1 downto 0));  
end leftshift;

architecture behaviour of leftshift is
begin

y(width-1 downto 1)<=d(width-2 downto 0);
y(0)<='0';

end behaviour;


-- keeps bit 0 (sticky) the same
entity sticky_leftshift is
    generic(width : positive);
    port(d : in bit_vector(width-1 downto 0);
         y : out bit_vector(width-1 downto 0));  
end sticky_leftshift;

architecture behaviour of sticky_leftshift is
begin

y(width-1 downto 2)<=d(width-2 downto 1);
y(0)<=d(1);
y(1)<='0';

end behaviour;