reg_file_256x32.vhd

DLX CPU VHDL CODE UNIVERSITY

--
-- $RCSfile: reg_file_256x32.vhd,v $
-- $Revision: 1.4 $
-- $Author: petera $
-- $Date: 90/05/28 14:27:49 $
--

use work.dp32_types.all;

entity reg_file_256x32 is
  generic (Tpd : Time := unit_delay;
      	   Tac : Time := unit_delay);
  port (a1 : in bit_8;
  	q1 : out bus_bit_32 bus;
	en1 : in bit;
	a2 : in bit_8;
	q2 : out bus_bit_32 bus;
	en2 : in bit;
	a3 : in bit_8;
	d3 : in bit_32;
	en3 : in bit);
end reg_file_256x32;

architecture behaviour of reg_file_256x32 is
  
begin

  reg_file: process (a1, en1, a2, en2, a3, en3)

    type register_array is array (reg_addr) of bit_32;
    variable registers : register_array;

  begin
    if en3 = '1' then
      registers(bit_8_to_reg_addr(a3)) := d3;
    end if;
    if en1 = '1' then
      q1 <= registers(bit_8_to_reg_addr(a1)) after Tac;
    else
      q1 <= null after Tpd;
    end if;
    if en2 = '1' then
      q2 <= registers(bit_8_to_reg_addr(a2)) after Tac;
    else
      q2 <= null after Tpd;
    end if;
  end process reg_file;

end behaviour;