geq.vhd

DLX CPU VHDL CODE UNIVERSITY

library IEEE;
use STD.textio.all;
use IEEE.std_logic_1164.all;
use work.dp32_types.all;

entity geq is
    generic(width: positive);
    port(a,b :in bit_vector(width-1 downto 0);
         y: out bit);
end geq;

architecture struture of geq is

begin
main : process(a,b)
begin
--wait for 1 ns;
if(bits_to_uint(a)<bits_to_uint(b))then
  y<='0';
else
  y<='1';
end if;

end process;
end;