fp_utils.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;

entity fp_is_zero is
   generic(width: positive);
   port ( fp: in bit_vector(width-1 downto 0);
	  r: out bit);
end fp_is_zero;

architecture behaviour of fp_is_zero is
begin

main : process (fp)

variable count : natural:=0;
begin

for i in width-1 downto 0 loop

if (fp(i)='0') then
  count:=count+1;
end if;

if (count=width) then
 r<='1';
else
 r<='0';
end if;


end loop;

end process;

end behaviour;