signext_16_32.vhd

DLX CPU VHDL CODE UNIVERSITY

--
-- $RCSfile: signext_8_32.vhd,v $
-- $Revision: 1.1 $
-- $Author: petera $
-- $Date: 90/05/17 16:10:58 $
--

use work.dp32_types.all;

entity signext_16_32 is
  generic (Tpd : Time := unit_delay);
  port (a : in bit_16;
      	b : out bus_bit_32 bus;
	en : in bit);
end signext_16_32;

architecture behaviour of signext_16_32 is

begin

  b_driver: process (en, a)
  begin
    if en = '1' then
      b(15 downto 0) <= a after Tpd;
      if a(15) = '1' then
      	b(31 downto 16) <= X"FF_FF" after Tpd;
      else
      	b(31 downto 16) <= X"00_00" after Tpd;
      end if;
    else
      b <= null after Tpd;
    end if;
  end process b_driver;

end behaviour;