latch.vhd

DLX CPU VHDL CODE UNIVERSITY

--
-- $RCSfile: latch.vhd,v $
-- $Revision: 1.1 $
-- $Author: petera $
-- $Date: 90/06/20 16:02:34 $
--

use work.dp32_types.all;

entity latch is
  generic (width : positive;
      	    Tpd : Time := unit_delay);
  port (d : in bit_vector(width-1 downto 0);
      	q : out bit_vector(width-1 downto 0);
	en : in bit);
end latch;

architecture behaviour of latch is

begin 

  process (d, en)
  begin
    if en = '1' then
      q <= d after Tpd;
    end if;
  end process;

end behaviour;