shifter.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;



entity shifter is
  generic (Tpd : Time := unit_delay);
  port (operand : in bit_32;
        result : out bus_bit_32 bus;
	amount : in bit_5;
	command : in bit_2);
end shifter;



architecture behaviour of shifter is
  
begin

  shifter_function: process (operand,amount , command)

    variable a : integer;
     variable temp_result, z : bit_32 := X"0000_0000";
     variable ones : bit_32 := X"FFFF_FFFF";  
  begin
    a:=bits_to_uint(amount);
    temp_result:=z;  
    case command is
      when "00" => -- LL
	for i in a to 31 loop
	  temp_result(i):=operand(i-a);
	end loop;
      when "01" => -- RA
        if ( operand(31)='1' ) then
	  temp_result := ones;
	end if;
	for i in 0 to (31-a) loop
	  temp_result(i):=operand(i+a);
	end loop;

      when "10" => -- RL
	for i in 0 to (31-a) loop
	  temp_result(i):=operand(i+a);
	end loop;
      when others =>

    end case;
  result<=temp_result after Tpd;
  end process shifter_function;
  
end behaviour;