link2.vhd

DLX CPU VHDL CODE UNIVERSITY

library IEEE;
use STD.textio.all;
use IEEE.std_logic_1164.all;
use work.dp32_types.all;


entity L32to64 is
    port(a,b :in bit_vector(31 downto 0);
         y: out bit_vector(63 downto 0));
end L32to64;
architecture structure of L32to64 is
begin

	y<=a&b;
end;