if_unit.vhd

DLX CPU VHDL CODE UNIVERSITY

library IEEE;
--use STD.textio.all;
use IEEE.std_logic_1164.all;
use work.dp32_types.all;


entity IF_Unit is
    generic (Tpd : Time := unit_delay);
    port (d : in bit_32;
          q1, q2 : out bus_bit_32 bus;
	  
	  j : in bit;
          jwa : in bit;
	  oe1, oe2: in bit;
          reset : in bit;
          PC_incr : in bit;
          phi1, phi2 : in bit
    );
end IF_Unit;


architecture behaviour of IF_Unit is
  
begin

  process --(d, oe, PC_incr, reset, j, phi1, phi2)
    variable master_PC, slave_PC : bit_32;
    variable reset_flag: bit:='0';
    
  begin
    wait until phi1 = '1'; 
    wait for 5 ns;
    if PC_incr = '1' then
    --wait on phi1; --until (read = '1' or write ='1');
     if(reset_flag='0') then
       slave_PC:=add(slave_PC,4);
     else
       reset_flag :='0';
     end if; 
    end if;

    

    if reset = '1' then
      slave_PC := X"0000_0000";
      reset_flag:='1';
    end if;    

    wait until phi1 = '0';

    if (jwa='1') then
      reset_flag:='1';
    end if;    

    if oe1 = '1' then
      q1 <= slave_PC after Tpd;
    else
      q1 <= null after Tpd;
    end if;
    if oe2 = '1' then
      q2 <= slave_PC after Tpd;
    else
      q2 <= null after Tpd;
    end if;
 
    wait until phi2='1';


    if j='1' then 
      slave_PC:=d;
    end if;

  end process;

end behaviour;