multdiv.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;

entity multdiv is
  generic (Tpd : Time := unit_delay);
  port (phi1, phi2 : in bit;
	operand1 : in bit_32;
      	operand2 : in bit_32;
	result : out bus_bit_32 bus;
	command : in bit_2);
end multdiv;

architecture behaviour of multdiv is



begin

  ALU_function: process (operand1, operand2, command)

    variable a, b : integer;
     variable temp_result : bit_32;
    variable Z,N :bit;


    constant divide :  bit_2 := "00";
    constant multiply: bit_2 := "01";
    constant divide_u :  bit_2 := "10";
    constant multiply_u: bit_2 := "11";


  begin
    case command is
      when  multiply | divide =>
      	a := bits_to_int(operand1);
      	b := bits_to_int(operand2);
      when  divide_u | multiply_u=>
        a := bits_to_uint(operand1);
        b := bits_to_uint(operand2);
      
    end case;
    case command is
     
      when multiply | multiply_u=>
      	if ((a>0 and b>0) or (a<0 and b<0))  -- result positive
	    and (abs a > integer'high / abs b) then  -- positive overflow
	  int_to_bits(integer'high, temp_result);

	elsif ((a>0 and b<0) or (a<0 and b>0))  -- result negative
      	    and ((- abs a) < integer'low / abs b) then  -- negative overflow
	  int_to_bits(integer'low, temp_result);

	else
	  int_to_bits(a * b, temp_result);

	end if;
      when divide | divide_u=>
      	if b=0 then
	  if a>=0 then 			  -- positive overflow
	    int_to_bits(integer'high, temp_result);
	  else
	    int_to_bits(integer'low, temp_result);
	  end if;

	else
	  int_to_bits(a / b, temp_result);
	
	end if;
     


    end case;

  result<=temp_result;

  end process ALU_function;
  
end behaviour;