fp_rounder.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;


--*********this divider is ment to divide mantissas, if the width is 3
--for example, and the answer is 100, the answer is actually 1.00
--ie, there is a decmil place after the first digit.
entity fp_rounder is
  generic(width : positive);
  port ( rnd: in bit_2;
	 sign : in bit;
	 mant_in: in bit_vector(width-1 downto 0);
	 mant_out: out bit_vector(width-1 downto 0);
	 incr_exp: out bit
	);
  end fp_rounder;


architecture behaviour of fp_rounder is

    constant rn : bit_vector(1 downto 0) := "00";
    constant rz : bit_vector(1 downto 0) := "01";
    constant rm : bit_vector(1 downto 0) := "10";
    constant rp : bit_vector(1 downto 0) := "11";
begin

main : process (rnd,mant_in)
    variable carry:bit;
    variable i: integer;

begin

case rnd is

 when rn =>
  if (mant_in(2)='1' and (mant_in(0)='1' or mant_in(3)='1')) then
   i:=0;
    for x in 2 to width-1 loop
      if(mant_in(x)='1') then
	i:=i+1;
      end if;
  
    end loop;
    if (i=width-2) then  -- overflow
      incr_exp<='1';
      for x in 2 to width-2 loop
        mant_out(x)<='0';
      end loop;
      mant_out(width-1)<='1';
    else 
      incr_exp<='0';
      carry:='1';
      for x in 3 to width-1 loop
        if(carry='1') then
         if (mant_in(x)='1') then
          mant_out(x)<='0';
         else 
          mant_out(x)<='1';
          carry:='0';
         end if;
        else 
         mant_out(x)<=mant_in(x);
        end if;
  

      end loop;
    end if;

  end if;
 when rz =>
	mant_out<=mant_in;
  -- do nothing, just truncate
 when rm =>

   if (sign='1' and (mant_in(0)='1' or mant_in(2)='1')) then
 ASSERT false REPORT vector_to_string(mant_in)  SEVERITY warning;             	
    ASSERT false REPORT "rm"  SEVERITY warning; 
  i:=0;
    for x in 2 to width-1 loop
      if(mant_in(x)='1') then
	i:=i+1;
      end if;
  
    end loop;
    if (i=width-2) then  -- overflow
      incr_exp<='1';
      for x in 2 to width-2 loop
        mant_out(x)<='0';
      end loop;
      mant_out(width-1)<='1';
    else 
      incr_exp<='0';
      carry:='1';
      for x in 3 to width-1 loop
        if(carry='1') then
         if (mant_in(x)='1') then
          mant_out(x)<='0';
         else 
          mant_out(x)<='1';
          carry:='0';
         end if;
        else 
         mant_out(x)<=mant_in(x);
        end if;
  

      end loop;
    end if;
  else
  mant_out<=mant_in;
  end if;
 when rp =>

    ASSERT false REPORT "rp"  SEVERITY warning; 

   if (sign='0' and (mant_in(0)='1' or mant_in(2)='1')) then
   	
   i:=0;
    for x in 2 to width-1 loop
      if(mant_in(x)='1') then
	i:=i+1;
      end if;
  
    end loop;
    if (i=width-2) then  -- overflow
      incr_exp<='1';
      for x in 2 to width-2 loop
        mant_out(x)<='0';
      end loop;
      mant_out(width-1)<='1';
    else 
      incr_exp<='0';
      carry:='1';
      for x in 3 to width-1 loop
        if(carry='1') then
         if (mant_in(x)='1') then
          mant_out(x)<='0';
         else 
          mant_out(x)<='1';
          carry:='0';
         end if;
        else 
         mant_out(x)<=mant_in(x);
        end if;
  

      end loop;
    end if;
  else
  mant_out<=mant_in;

  end if;
end case;

end process;

end behaviour;