divider.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;


--*********this divider is ment to divide mantissas, if the width is 3
--for example, and the answer is 100, the answer is actually 1.00
--ie, there is a decmil place after the first digit.

entity divider is
    generic (width : positive);
    port(q,d : in bit_vector(width-1 downto 0);
         y: out bit_vector(width+2 downto 0);
	 r : out bit);
end divider;


architecture behaviour of divider is
begin

main : process (q,d)

variable Y2: bit_vector(width+2 downto 0);
variable Qt: bit_vector(width+3 downto 0);
variable dt: bit_vector(width+2 downto 0);
variable Q2 : bit_vector(width+3 downto 0);
variable c: natural :=0;


begin

Q2(width+3):='0';
Q2(0):='0';
Q2(1):='0';
Q2(2):='0';
Q2(width+2 downto 3):=q;

dt(0):='0';
dt(1):='0';
dt(2):='0';
dt(width+2 downto 3):=d;


for i in 0 to (width+2) loop
  if(bits_to_uint(dt) > bits_to_uint(Q2)) then
    Y2(width+2-i):='0';
  else 
    int_to_bits(bits_to_uint(Q2)-bits_to_uint(dt),Qt);
    Q2:=Qt;
    Y2(width+2-i):='1';    
  end if;

  --shift q2 left
  for u in width+3 downto 1 loop
    Q2(u):=Q2(u-1);    
  end loop;
  Q2(0):='0';

end loop;

if (bits_to_uint(dt)=0) then
 Y2(0):='0';
else
 r<='1'; -- remainder bit is set 
 Y2(0):='1'; --stick bit is set because of remainder
end if;

y<=Y2;

end process;

end behaviour;