mux2.vhd

DLX CPU VHDL CODE UNIVERSITY

--
-- $RCSfile: mux2.vhd,v $
-- $Revision: 1.1 $
-- $Author: petera $
-- $Date: 90/06/21 10:12:27 $
--

use work.dp32_types.all;

entity mux2 is
  generic (width : positive;
      	    Tpd : Time := unit_delay);
  port (i0, i1 : in bit_vector(width-1 downto 0);
      	y : out bit_vector(width-1 downto 0);
	sel : in bit);
end mux2;

architecture behaviour of mux2 is
begin
  with sel select
    y <=  i0 after Tpd when '0',
      	  i1 after Tpd when '1';
end behaviour;







entity bitmux2 is
  port (i0, i1 : in bit;
      	y : out bit;
	sel : in bit);
end bitmux2;

architecture behaviour of bitmux2 is
begin
  with sel select
    y <=  i0  when '0',
      	  i1  when '1';
end behaviour;