fp_div_create_flags.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;



entity create_flags is
    port (nan, z, v,u,n: in bit;
	  flags : out bit_7);
end create_flags;


architecture behaviour of divider is
begin

main:process (nan,z,v,u,n)

flags<="0000000";
flags(1)<=nan;
flags(4)<=z;
flags(5)<=v;
flags(6)<=u;
flags(7)<=n;

end process;



end behaviour;