fp_div.vhd

DLX CPU VHDL CODE UNIVERSITY

Library IEEE;            
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_unsigned.all; 
use work.all;
use work.dp32_types.all;




entity fp_div is
  generic( simulation_delay : time := 10 ns );
  port( phi1,phi2: in bit;
	Op1, Op1b, Op2, Op2b : in bit_32;
	R, Rb : inout bit_32;
	op : in bit_2;
	fsr_in : in bit_32;
	fsr_out : out bit_32 );
end fp_div;


architecture structural of fp_div is 

  component fp_rounder 
  generic(width : positive);
  port ( rnd: in bit_2;
	 sign : in bit;
	 mant_in: in bit_vector(width-1 downto 0);
	 mant_out: out bit_vector(width-1 downto 0);
	 incr_exp: out bit
	);
  end component;


  component fp_is_zero
   generic(width: positive);
   port ( fp: in bit_vector(width-1 downto 0);
	  r: out bit);
  end component;


  component create_flags
    port (nan, z, v,u,n: in bit;
	  flags : out bit_5);
  end component;


  component flags_replace
    port (fsr_in : in bit_32;
	  fsr_out : out bit_32;
	  flags : in bit_5);
  end component;

  component mux2
    generic (width : positive);
    port (i0, i1 : in bit_vector(width-1 downto 0);
      	  y : out bit_vector(width-1 downto 0);
	  sel : in bit);
  end component;

  component bitmux2
    port (i0, i1 : in bit;
      	  y : out bit;
	  sel : in bit);
  end component;

  component divider
    generic (width : positive);
    port(q,d : in bit_vector(width-1 downto 0);
         y: out bit_vector(width+2 downto 0);
         r : out bit);
end component;	 

  component g_xor

    generic(width : positive);
    port(a,b : in bit_vector(width-1 downto 0);
         y : out bit_vector(width-1 downto 0));  
end component;

  component g_xor_b
    port(a,b : in bit;
         y : out bit);
end component;

  component sticky_leftshift
    generic(width : positive);
    port(d : in bit_vector(width-1 downto 0);
         y : out bit_vector(width-1 downto 0));  
end component;

  component subtractor_signed
    generic (width : positive);
    port(a,b : in bit_vector(width-1 downto 0);
         y : out bit_vector(width-1 downto 0);
	 n,z : out bit);
end component;

  component adder_signed
    generic(width : positive);
    port(a,b : in bit_vector(width-1 downto 0);
         y : out bit_vector(width-1 downto 0);
	 o : out bit);
end component;

  component subtractor_unsigned
    generic (width : positive);
    port(a,b : in bit_vector(width-1 downto 0);
         y : out bit_vector(width-1 downto 0);
	 n,z : out bit);
end component;

  component adder_unsigned
    generic(width : positive);
    port(a,b : in bit_vector(width-1 downto 0);
         y : out bit_vector(width-1 downto 0);
	 o : out bit);
end component;

  component g_or
    generic(width : positive);
    port(a,b : in bit_vector(width-1 downto 0);
         y: out bit_vector(width-1 downto 0));
end component;

  component bit_or
    port(a,b : in bit;
         y: out bit);
end component;

  component geq
    generic(width: positive);
    port(a,b :in bit_vector(width-1 downto 0);
         y: out bit);
end component;

component mant_ext
    generic(width: positive);
    port(a :in bit_vector(width-1 downto 0);
         y: out bit_vector(width-1 downto 0));
end component;

component mant_cut
    generic(width: positive);
    port(a :in bit_vector(width-1 downto 0);
         y: out bit_vector(width-5 downto 0));
end component;




 component L32to64
    port(a,b :in bit_32;
         y: out bit_64);
end component;

 component L64to32
    port(a :in bit_64;
         r1 : out bit_32;
	 y2: out bit_32);
end component;

 ---signal x, d: bit_53;
 --signal q: bit_53;
    signal dOp1, dOp2: bit_64;   
    signal dR: bit_64;
    signal rdl: bit_32;

    constant idel: bit_2 :="00";
    constant div:       bit_2  :="01";
    constant divd:       bit_2  :="11";

    signal d_flags, s_flags : bit_5;


--    alias Underflow

    subtype mant_l is bit_27;
    subtype mant is bit_24;
    subtype exp is bit_8;
    subtype dmant is bit_53;
    subtype dmant_l is bit_56;
    subtype dexp is bit_11;
    signal r_sign_b, dr_sign_b: bit;
    signal s_inv, s_v, s_dz, s_u, s_ix : bit;
    signal d_inv, d_v, d_dz, d_u, d_ix : bit;
    signal nowhere : bit;
    signal mux_sel : bit;
    signal either_overflow : bit;
    signal  temp_mant : mant_l;
    signal  temp_exp : exp;
    signal  temp_exp_w_bias : exp;
    signal  temp_exp_w_bias_and_1 : exp;
    signal  temp_mant_redid : mant_l;  
    signal  bias : exp := b"01111111"; 
    signal  exp_overflow : bit;    
    signal  exp_overflow_2 : bit;
--    signal  remdr : bit;
    signal  null2 : mant;
    signal  value_of_one_bit_27 : mant_l:= b"100000000000000000000000000";
    signal  value_N_one_8_bit : exp := b"00000001";
    signal  ea_mant: mant;
    signal  eb_mant: mant;
    signal  try : mant;
    signal  r_mant_almost : mant_l;
    signal  r_mant_rounded : mant_l;
    signal  rf: bit_32;
    signal new_flags: bit_5;
    signal dnowhere : bit;
    signal dmux_sel : bit;
    signal deither_overflow : bit;
    signal  dtemp_mant : dmant_l;
    signal  dtemp_exp : dexp;
    signal  dtemp_exp_w_bias : dexp;
    signal  dtemp_exp_w_bias_and_1 : dexp;
    signal  dtemp_mant_redid : dmant_l;  
    signal  dbias : dexp := b"01111111111"; 
    signal  dexp_overflow : bit;    
    signal  dexp_overflow_2 : bit;
--    signal  dremdr : bit;
    signal  dnull2 : dmant;
    signal  value_of_one_bit_56 : dmant_l:= b"10000000000000000000000000000000000000000000000000000000";
    signal  value_N_one_11_bit : dexp := b"00000000001";
    signal  dea_mant: dmant;
    signal  deb_mant: dmant;
    signal  dtry : dmant;
    signal  dr_mant_almost : dmant_l;
    signal  dr_mant_rounded : dmant_l;
    signal  drf: bit_32;
    signal  add_to_exp, dadd_to_exp: bit;

    signal  temp: bit_vector(3 downto 0);  


    alias round_mode: bit_2 is fsr_in(31 downto 30);

    alias a_mant: mant is Op1(23 downto 0);
    alias b_mant: mant is Op2(23 downto 0);
    alias r_mant: bit_23 is rf(22 downto 0);
    alias a_exp: exp is Op1(30 downto 23);
    alias b_exp: exp is Op2(30 downto 23);
    alias r_exp: exp is rf(30 downto 23);
    alias a_sign: bit_1 is Op1(31 downto 31);
    alias b_sign: bit_1 is Op2(31 downto 31);
    alias a_sign_b: bit is Op1(31);
    alias b_sign_b: bit is Op2(31);
    alias r_sign: bit_1 is rf(31 downto 31);
   -- alias r_sign_b: bit is R(31);


    alias da_mant: dmant is dOp1(52 downto 0);
    alias db_mant: dmant is dOp2(52 downto 0);
    alias dr_mant: bit_52 is dR(51 downto 0);
    alias da_exp: dexp is dOp1(62 downto 52);
    alias db_exp: dexp is dOp2(62 downto 52);
    alias dr_exp: dexp is dR(62 downto 52);
    alias da_sign: bit_1 is dOp1(63 downto 63);
    alias db_sign: bit_1 is dOp2(63 downto 63);
    alias da_sign_b: bit is dOp1(63);
    alias db_sign_b: bit is dOp2(63);
    alias dr_sign: bit_1 is dR(63 downto 63); 
    --alias dr_sign_b: bit is Rb(31);




-- op (1) set means double precision
begin

--  dOp1:=Op1b&Op1;


  op1in : L32to64
    port map(a=>Op1b,b=>Op1,
         y=>dOp1);

  op2in : L32to64
    port map(a=>Op2b,b=>Op2,
         y=>dOp2);

   rmaker : L64to32
     port map(a=>dR,
         r1=>Rb,
         y2=>rdl);


  a_ext :  mant_ext
    generic map (width=>24 )
    port map(a =>a_mant,
         y=>ea_mant);

   b_ext :  mant_ext
    generic map (width=>24 )
    port map(a =>b_mant,
        y=>eb_mant);
   
   da_ext :  mant_ext
    generic map (width=>53 )
    port map(a =>da_mant,
         y=>dea_mant);

   db_ext :  mant_ext
    generic map (width=>53 )
    port map(a =>db_mant,
        y=>deb_mant);
  
   abdiv : divider
    generic map (width=>24)
    port map (q => ea_mant, d => eb_mant, y => temp_mant,
	      r => s_ix);


   dabdiv : divider
    generic map (width=>53)
    port map (q => dea_mant, d => deb_mant, y => dtemp_mant,
	      r => d_ix);


  mantshifet : sticky_leftshift
    generic map (width=>27)
    port map (d => temp_mant, y => temp_mant_redid);

  dmantshifet : sticky_leftshift
    generic map (width=>56)
    port map (d => dtemp_mant, y => dtemp_mant_redid);
 
  
  abadd : subtractor_unsigned
    generic map (width=>8)
    port map(a=>a_exp,b=>b_exp,
         y=>temp_exp, 
	 n=>s_u,
	 z=>nowhere);

  dabadd : subtractor_unsigned
    generic map (width=>11)
    port map(a=>da_exp,b=>db_exp,
         y=>dtemp_exp, 
	 n=>d_u,
	 z=>dnowhere);
 
   comp :  geq
    generic map (width=>27)
    port map(a=>temp_mant,
	 b=>value_of_one_bit_27,
         y=>mux_sel);

   dcomp :  geq
    generic map (width=>56)
    port map(a=>dtemp_mant,
	 b=>value_of_one_bit_56,
         y=>dmux_sel);


  sign_gen :  g_xor
    generic map (width =>1)
    port map (a=>a_sign,b=>b_sign,
         y=>r_sign);

  dsign_gen :  g_xor
    generic map (width =>1)
    port map (a=>da_sign,b=>db_sign,
         y=>dr_sign);

  sign_gen_b :  g_xor_b
    port map (a=>a_sign_b,b=>b_sign_b,
         y=>r_sign_b);

  dsign_gen_b :  g_xor_b
    port map (a=>da_sign_b,b=>db_sign_b,
         y=>dr_sign_b);

  bias_add :  adder_unsigned
    generic map(width =>8)
    port map(a=>temp_exp,
	 b=>bias,
         y=>temp_exp_w_bias,
	 o=>exp_overflow);


  dbias_add :  adder_unsigned
    generic map(width =>11)
    port map(a=>dtemp_exp,
	 b=>dbias,
         y=>dtemp_exp_w_bias,
	 o=>dexp_overflow);
  
  one_add : adder_unsigned
    generic map(width=>8)	
    port map(a=>value_n_one_8_bit,
	     b=>temp_exp_w_bias,
	     y=>temp_exp_w_bias_and_1,
	     o=>exp_overflow_2);

  done_add : adder_unsigned
    generic map(width=>11)	
    port map(a=>value_n_one_11_bit,
	     b=>dtemp_exp_w_bias,
	     y=>dtemp_exp_w_bias_and_1,
	     o=>dexp_overflow_2);


  exp_mux: mux2
    generic map(width =>8)
    port map (i0=>temp_exp_w_bias_and_1,
	  i1=>temp_exp_w_bias,
      	  y=>r_exp,
	  sel=>mux_sel);

  dexp_mux: mux2
    generic map(width =>11)
    port map (i0=>dtemp_exp_w_bias_and_1,
	  i1=>dtemp_exp_w_bias,
      	  y=>dr_exp,
	  sel=>dmux_sel);


  mant_mux: mux2
    generic map(width =>27)
    port map (i0=>temp_mant_redid,
	  i1=>temp_mant,
      	  y=>r_mant_almost,
	  sel=>mux_sel);

  dmant_mux: mux2
    generic map(width =>56)
    port map (i0=>dtemp_mant_redid,
	  i1=>dtemp_mant,
      	  y=>dr_mant_almost,
	  sel=>dmux_sel);

  round: fp_rounder 
  generic map(width=>27)
  port map( rnd=>round_mode,
	 sign=>r_sign_b,
	 mant_in=>r_mant_almost,
	 mant_out=>r_mant_rounded,
	 incr_exp=>add_to_exp
	);

  dround: fp_rounder 
  generic map(width=>56)
  port map( rnd=>round_mode,
	 sign=>dr_sign_b,
	 mant_in=>dr_mant_almost,
	 mant_out=>dr_mant_rounded,
	 incr_exp=>dadd_to_exp
	);


   cutter :  mant_cut
    generic map (width=>27 )
    port map(a =>r_mant_rounded,
        y=>r_mant);
  

   dcutter :  mant_cut
    generic map (width=>56 )
    port map(a =>dr_mant_rounded,
        y=>dr_mant);
  

  overflow_mux: bitmux2
    port map (i0=>either_overflow,
	  i1=>exp_overflow,
	  y=>s_v,
	  sel=>mux_sel);

  doverflow_mux: bitmux2
    port map (i0=>deither_overflow,
	  i1=>dexp_overflow,
	  y=>d_v,
	  sel=>dmux_sel);



  overflow_gen :  bit_or
    port map (a=>exp_overflow,b=>exp_overflow_2,
         y=>either_overflow);


  doverflow_gen :  bit_or
    port map (a=>dexp_overflow,b=>dexp_overflow_2,
         y=>deither_overflow);

  insert_flags : flags_replace
    port map(fsr_in=>fsr_in,
	  fsr_out=>fsr_out,
	  flags=>new_flags);



  out_mux: mux2
    generic map(width =>32)
    port map (i0=>rf,
	  i1=>rdl,
      	  y=>R,
	  sel=>op(1));


  dz_s: fp_is_zero
   generic map (width=>32)
   port map ( fp=>Op2 ,
	  r=>s_dz);

  dz_d: fp_is_zero
   generic map (width=>64)
   port map( fp=>dOp2 ,
	  r=>d_dz);


  flags_s: create_flags
    port map(nan=> s_inv ,
	      z=> s_v ,
	      v=> s_u  ,
	      u=> s_dz  ,
	      n=> s_ix  ,
	      flags=> s_flags );
  

  flags_d: create_flags
    port map(nan=> d_inv ,
	      z=> d_v ,
	      v=> d_u  ,
	      u=> d_dz  ,
	      n=> d_ix  ,
	      flags=> d_flags );
  

  out_flags_mux: mux2
    generic map(width =>5)
    port map (i0=>s_flags,
	  i1=>d_flags,
      	  y=>new_flags,
	  sel=>op(1));



end structural;