alu_32.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all, work.ALU_32_types.all;

entity ALU_32 is
  generic (Tpd : Time := unit_delay);
  port (operand1 : in bit_32;
      	operand2 : in bit_32;
	result : out bus_bit_32 bus;
	cond_code : out CC_bits;
	command : in bit_5);
end ALU_32;

architecture behaviour of ALU_32 is

  alias cc_V : bit is cond_code(2);
  alias cc_N : bit is cond_code(1);
  alias cc_Z : bit is cond_code(0);



begin

  ALU_function: process (operand1, operand2, command)

    variable a, b : integer;
     variable temp_result : bit_32;
    variable Z,N :bit;


constant disable : bit_5 := "00000";
constant pass1   : bit_5 := "00001";
constant incr1   : bit_5 := "00010";
constant add     : bit_5 := "00011";
constant subtract: bit_5 := "00100";
constant log_and : bit_5 := "00101";
constant log_or  : bit_5 := "00110";
constant log_xor : bit_5 := "00111";
constant log_mask: bit_5 := "01000";
constant incr4   : bit_5 := "01001";
constant incr8   : bit_5 := "01010";
constant add_u   : bit_5 := "01011";
constant subtract_u:bit_5:= "01100";
constant seq	 : bit_5 := "01101";
constant sge	:  bit_5 := "01110";
constant sgt	:  bit_5 := "01111";
constant sle	:  bit_5 := "10000";
constant sll	:  bit_5 := "10001";
constant slt    :  bit_5 := "10010";
constant sne    :  bit_5 := "10011";
constant sra    :  bit_5 := "10100";
constant srl    :  bit_5 := "10101";
constant divide_u: bit_5 := "10110";
constant multiply_u:bit_5:= "10111";
constant divide :  bit_5 := "11000";
constant multiply: bit_5 := "11001";







  begin
    case command is
      when add | subtract | multiply | divide | sne | seq | sge | sgt
| sle | slt=>
      	a := bits_to_int(operand1);
      	b := bits_to_int(operand2);
      when add_u | subtract_u | divide_u | multiply_u=>
        a := bits_to_uint(operand1);
        b := bits_to_uint(operand2);
      when incr1 =>
      	a := bits_to_int(operand1);
      	b := 1;
      when incr4 =>
        a := bits_to_int(operand1);
        b := 4;
      when incr8 =>
	a:= bits_to_int(operand1);
	b:=8;	
      when others =>
      	null;
    end case;
    case command is
      when disable =>
      	null;
      when pass1 =>
      	temp_result := operand1;
      when log_and =>
       	temp_result := operand1 and operand2;
      when log_or =>
       	temp_result := operand1 or operand2;
      when log_xor =>
       	temp_result := operand1 xor operand2;
      when log_mask =>
       	temp_result := operand1 and not operand2;
      when add | incr8| incr1 | incr4 | add_u =>
      	if b > 0 and a > integer'high-b then  -- positive overflow
	  int_to_bits(((integer'low+a)+b)-integer'high-1, temp_result);
	  cc_V <= '1' after Tpd;
	elsif b < 0 and a < integer'low-b then  -- negative overflow
	   int_to_bits(((integer'high+a)+b)-integer'low+1, temp_result);
	  cc_V <= '1' after Tpd;
	else
	  int_to_bits(a + b, temp_result);
	  cc_V <= '0' after Tpd;
	end if;
      when subtract | subtract_u | sne | seq | sge | sgt | sle | slt=>
      	if b < 0 and a > integer'high+b then  -- positive overflow
	  int_to_bits(((integer'low+a)-b)-integer'high-1, temp_result);
	  cc_V <= '1' after Tpd;
	elsif b > 0 and a < integer'low+b then  -- negative overflow
	  int_to_bits(((integer'high+a)-b)-integer'low+1, temp_result);
	  cc_V <= '1' after Tpd;
	else
	  int_to_bits(a - b, temp_result);
	  cc_V <= '0' after Tpd;
	end if;
      when multiply | multiply_u=>
      	if ((a>0 and b>0) or (a<0 and b<0))  -- result positive
	    and (abs a > integer'high / abs b) then  -- positive overflow
	  int_to_bits(integer'high, temp_result);
	  cc_V <= '1' after Tpd;
	elsif ((a>0 and b<0) or (a<0 and b>0))  -- result negative
      	    and ((- abs a) < integer'low / abs b) then  -- negative overflow
	  int_to_bits(integer'low, temp_result);
	  cc_V <= '1' after Tpd;
	else
	  int_to_bits(a * b, temp_result);
	  cc_V <= '0' after Tpd;
	end if;
      when divide | divide_u=>
      	if b=0 then
	  if a>=0 then 			  -- positive overflow
	    int_to_bits(integer'high, temp_result);
	  else
	    int_to_bits(integer'low, temp_result);
	  end if;
	  cc_V <= '1' after Tpd;
	else
	  int_to_bits(a / b, temp_result);
	  cc_V <= '0' after Tpd;

	end if;
     when others =>  


    end case;

    if command /= disable then
      result <= temp_result after Tpd;
    else
      result <= null after Tpd;
    end if;
    Z := bool_to_bit(temp_result = X"00000000");
    cc_Z <=Z after Tpd;
    N := bool_to_bit(temp_result(31) = '1');
    cc_N <=N after Tpd;
    if(command=sne) then
      if (Z='1') then
        result<=X"0000_0000";
      else
	result<=X"0000_0001";
      end if;	
    end if;

    if(command=sge) then
      if (N='1') then
        result<=X"0000_0001";
      else
	result<=X"0000_0000";
      end if;	
    end if;

    if(command=slt) then
      if (N='1') then
        result<=X"0000_0000";
      else
	result<=X"0000_0001";
      end if;	
    end if;

    if(command=seq) then
      if (Z='1') then
        result<=X"0000_0001";
      else
	result<=X"0000_0000";
      end if;	
    end if;

    if(command=sgt) then
      if (Z='1' or N='0') then
        result<=X"0000_0000";
      else
	result<=X"0000_0001";
      end if;	
    end if;

    if(command=sle) then
      if (Z='1' or N='1') then
        result<=X"0000_0001";
      else
	result<=X"0000_0000";
      end if;	
    end if;


  end process ALU_function;
  
end behaviour;