or.vhd

DLX CPU VHDL CODE UNIVERSITY

entity g_or is
    generic(width : positive);
    port(a,b : in bit_vector(width-1 downto 0);
         y: out bit_vector(width-1 downto 0));
end g_or;

architecture structure of g_or is

begin

y<=a or b;
end;



entity bit_or is

    port(a,b : in bit;
         y: out bit);
end bit_or;

architecture structure of bit_or is

begin
y<= a or b;
end;