dp32_entity.vhd

DLX CPU VHDL CODE UNIVERSITY

--
-- $RCSfile: dp32_entity.vhd,v $
-- $Revision: 1.2 $
-- $Author: petera $
-- $Date: 90/05/16 15:01:40 $
--

use work.dp32_types.all;

entity dp32 is
  generic
    (Tpd : Time := unit_delay);
  port (d_bus : inout bus_bit_32 bus;
      	a_bus : out bus_bit_32 bus;
	read, write : out bit;
	fetch : out bit;
	ready : in bit;
	phi1, phi2 : in bit;
	reset : in bit);
end dp32;