dp32_test.vhd

DLX CPU VHDL CODE UNIVERSITY

--
-- $RCSfile: dp32_test.vhd,v $
-- $Revision: 1.2 $
-- $Author: petera $
-- $Date: 90/05/25 16:35:09 $
--

----------------------------------------------------------------
-- Clock Generator
----------------------------------------------------------------

use work.dp32_types.all;


entity clock_gen is
  generic
    (Tpw : Time:=50 ns;			  -- clock pulse width
     Tps : Time:=25 ns);			  -- pulse separation between phases
  port (phi1, phi2 : out bit;
	reset : out bit);
end clock_gen;

architecture behaviour of clock_gen is

  constant clock_period : Time := 2*(Tpw+Tps);
  
begin

  reset_driver :
    reset <=
      '1',
      '0' after 2*clock_period+Tpw;
  
  clock_driver : process
  begin
    phi1 <= 
      '1', 
      '0' after Tpw;
    phi2 <=
      '1' after Tpw+Tps,
      '0' after Tpw+Tps+Tpw;
    wait for clock_period;
  end process clock_driver;
  
end behaviour;

----------------------------------------------------------------
-- dp32_test
----------------------------------------------------------------

use work.dp32_types.all;

entity dp32_test is
end dp32_test;

architecture structure of dp32_test is
  
  component clock_gen
    port (phi1, phi2 : out bit;
	  reset : out bit);
  end component;

  component dp32
    port (d_bus : inout bus_bit_32 bus;
      	  a_bus : out bus_bit_32 bus;
	  read, write : out bit;
	  fetch : out bit;
	  ready : in bit;
	  phi1, phi2 : in bit;
	  reset : in bit);
  end component;
  
  component memory
    port (phi1,phi2 : in bit;
	  a : in bus_bit_32 bus;
	  d : inout bus_bit_32 bus;
	  read : in bit;
	  write : in bit;
	  ready : out bit);
  end component;
  
  signal d_bus : bus_bit_32 bus;
  signal a_bus : bus_bit_32 bus;
  signal read, write : bit;
  signal fetch : bit;
  signal ready : bit;
  signal phi1, phi2 : bit;
  signal reset : bit;
  
begin

  cg : clock_gen
    port map (phi1 => phi1, phi2 => phi2, reset => reset);
    
  proc : dp32
    port map (d_bus => d_bus, a_bus => a_bus,
      	      read => read, write => write, fetch => fetch,
	      ready => ready,
	      phi1 => phi1, phi2 => phi2, reset => reset);
  
  mem : memory
    port map (phi1 => phi1, phi2 => phi2, a => a_bus, d => d_bus,
      	      read => read, write => write, ready => ready);

end structure;