documentation.txt

DLX CPU VHDL CODE UNIVERSITY

add -
nv  ?
of  s
uf  s
dz  x
nx  ?

mult-
nv  ?
of  s
uf  s
dz  x
nx  ?

div -
nv  ?
of  s
uf  s
dz  s
nx  s







Introduction:
	The DLX Microprocessor is a microprocessor in theory, to my
knowledge it has never been put onto silicon, at least for comercial
sale. It's main purpose is to study, teach, and practice with
microprocessor design. The Instruction set architecture is very
simmilar to MIPS, although there are differences. It is a load/store
architecture and is RISC.

Specific Information:
  Registers:
    General-Purpose:
      Number - 32
      Width - 32 bits
      Special attributes - R0 is always read as 0x00000000
    Floating point:
      Number - 32
      Width - 32 bits
      Special attributes - can refer to a pair of registers, the first
       being an even numberd one, as a 64 bit register for double
       precision operations
    Floating point status register:
      Width - 32 bits
      Similar to - SPARC Architecture FSR
        The SPARC ARCHITECTURE Manual, Version 8, by David L. Weaver
         and Tom Germond, 1992, ISBN 0-13-825001-4
      Format -    -31-30--29-28--27-23--22-13--12---11-10--9-5---4-0--
		 !  rd  |  u  |  tem  |   u  | jmp |  u | aexc | cexc |
		  ----------------------------------------------------
        rd - Rounding mode
          rn = Round Normal =   00
          rz = Round Zero =     01
          rm = Round Neg Inf =  10
          rp = Round Pos Inf =  11
        u - unused
        tem - template enable mask
          bits same as cexc and aexc fields
        jmp - set by the floating point comparison instructions, set
         if compareison is true
        aexc - accrued exceptions - same format as cexc
        cexc - current exception
          Format:  --4----3----2----1----0-
                  | nv | of | uf | dz | nx |
                   ------------------------
          Fields:
            nv - invalid operation
            of - overflow
            uf - underflow
            dz - division by zero
            nx - inexact
  Architecture -
   
  Compiling - The following compiler was used to generate simulation
   needed files:
      ModelSim EE/VHDL 5.1b Dec 28 1997 SunOS 5.5.1
       Copyright Mentor Graphics Corp 1982-1997
       Copyright Model Technology Inc 1990-1997
  
  Simulator -  The following simulator was used to simulate the processor:
      ModelSim EE/VHDL 5.1b Dec 28 1997 SunOS 5.5.1
       Copyright Mentor Graphics Corp 1982-1997
       Copyright Model Technology Inc 1990-1997




The following commands are supported. for more information on their
context, please see:
The DLX Instruction Set Architecture Handbook, by Philip M Sailer and
David R Kaeli, 1996 ISBN 1-55860-371-9
MULTF
MULTD
GTD
GED
LTD
LED
EQD
NED
GTF
GEF
LTF
LEF
EQF
NEF
BFPT
BFPF
MOVF
MOVD
CVTF2D
CVTF2I
CVTD2F
CVTD2I
CVTI2F
CVTI2D
ADDF
ADDD
SUBF
SUBD
LD
SD
LF
SF
LW	
SW	
ADD	
ADDU
ADDUI
ADDI	
BEQZ
BNEZ
SUB	
SUBU	
SUBI
SUBUI	
NOP	
AND	
ANDI	
OR 
ORI
XOR
XORI	
MULT 
MULTU
DIV  
DIVU 
J
JAL
JR
JALR
SEQ
SEQI
SNE
SNEI
SGE
SGEI
SLE
SLEI
SGT
SGTI
SLT
SLTI
SLL
SLLI
SRL
SRLI
SRA
SRAI

Non standard opcode used in this implimentation:
  Description:   Load the FSR from a GP register 
  Format :       Setfsr r1
  Binary :       100010b r1 000000000000000000000b




You can use the following sources to obtain more information on the
DLX Microprocessor:

The DLX Instruction Set Architecture Handbook, by Philip M Sailer and
David R Kaeli, 1996 ISBN 1-55860-371-9

Computer Architecture: A Quantitative Approch, 2nd edition, by John
L. Hennessy and David A. Patterson, 1995, ISBN 1-55860-329-8


Sources for some subunits of the processor:

FP Adder -  fp_adder.doc is the origional documentation it came with,
  slightly modified. The main changes made to the adder itself were
  double precision support, FSR useage, Rounding mode support,
  exception useage, and invalid operand detection.
  Here it the header it came with:
  -- Source:  Patterson, David A., and Hennessy, John L.,  "Computer 
  --	         architecture: a quantitative approach".  San Mateo, CA: Morgank
  --		 Kaufman Publishers, 1990,  Appendix A, p. 12-20
  -- Author: Bob McIlhenny 
  --	   University of California, Irvine, CA 92717
  -- 
  --	   based on an original design by:
  --	   Marc Rose, Intel Corporation
  --         
  -- Written on June 9, 1993
  --
  -- Modified by Jesse Pan on Nov 18, 1993


FP Multiplier -  FP_Mult.doc is the origional documentation it came with,
  slightly modified. The main changes made to the multiplier itself were
  double precision support, FSR useage, Rounding mode support,
  exception useage, and invalid operand detection.
  Here it the header it came with:
  -- Source:  Patterson, David A., and Hennessy, John L.,  "Computer
  --	         architecture: a quantitative approach".  San Mateo, CA: Morgan
  --		 Kaufman Publishers, 1990,  Appendix A, p. 3-22
  -- Author: Jesse Pan
  --	   Department of Electrical and Computer Engineering
  --	   University of California, Irvine, CA 92717
  --  
  -- Acknowledgement: Special thanks to Dr. Tomas Lang's advice on this benchmark
  --          
  -- Written on Feb 01, 1994
  --
  -- Verification Information:
  --
  --                  Verified     By whom?           Date         Simulator
  --                  --------   ------------        --------     ------------
  --  Syntax            yes     Jesse Pan	           01 Feb 94    Synopsys
  --  Functionality     yes     Jesse Pan	           01 Feb 94    Synopsys


Thanks to:
  Professor Mike Schulte  
  http://www.eecs.lehigh.edu/~mschulte/

  James E. Stine, Jr
  http://www.eecs.lehigh.edu/~jes6/

  National Science Foundation
  http://www.nsf.gov/