sqrmul.vhd

DLX CPU VHDL CODE UNIVERSITY

--This file was created using SQRMUL
--Written by Louis Marquette
[e-mail]
--http://www.starrtechnologies.com/louis/index.htm


entity adder is
port (A,B : in bit;
      R,C : out bit );
end adder;
architecture process of adder is
begin
  R<=A xor B after 2 ns;
  C<=A and B after 1 ns;
end process;
entity full_adder is
port (A,B,Ci : in bit;
      R,Co : out bit );
end full_adder;
architecture process of full_adder is
begin
  R<=(Ci or( (A or B)and (not (B and A) ) ) ) and  (not((
(A and B)or(not(A or B)) )  and Ci ) )   after 6 ns;
  C<=((Ci and ((A or B) and (not(A and B)) )  ) or(A and B) ) after 5 ns;
end process;
entity SQR is
port (A : in bit_vector(4 downto 0);
      R : out bit_vector(4 downto 0) );
end SQR;

architecture behaviour of SQR is
signal C1  : bit;
signal C1_1_2  : bit;
signal C1_2_3  : bit;
signal C1_3_4  : bit;
signal C2  : bit;
signal C2_1_2  : bit;
signal C2_2_3  : bit;
signal C3  : bit;
signal C3_1_2  : bit;
signal R1_1  : bit;
signal AND0_1  : bit;
signal AND0_2  : bit;
signal AND0_3  : bit;
signal AND0_4  : bit;
signal AND1_2  : bit;
signal AND1_3  : bit;
signal AND1_4  : bit;
signal AND2_3  : bit;
signal AND2_4  : bit;
signal AND3_4  : bit;
begin
AND0_1 := A(0) and A(1) after 1 ns;
AND0_2 := A(0) and A(2) after 1 ns;
AND0_3 := A(0) and A(3) after 1 ns;
AND0_4 := A(0) and A(4) after 1 ns;
AND1_2 := A(1) and A(2) after 1 ns;
AND1_3 := A(1) and A(3) after 1 ns;
AND1_4 := A(1) and A(4) after 1 ns;
AND2_3 := A(2) and A(3) after 1 ns;
AND2_4 := A(2) and A(4) after 1 ns;
AND3_4 := A(3) and A(4) after 1 ns;
--special cases
R(0) <= A(0);
R(1) <= '0';
--First Row
  --Last Add
    R(2)<=A(1) xor AND0_1 after 2 ns;
    C1_3_4:=A(1) AND0_1 after 1 ns;
end behaviour;