dp32_rtl.vhd

DLX CPU VHDL CODE UNIVERSITY

	  addr_latch_l : out bit;
	  name_signext_en : out bit;
	  shift_op : out bit_2;
	  shift_mux : out bit;
	  force_reg_31_dest : out bit;
	  multdiv_op:out bit_2;
	  fpadd_op:out bit_4;
	  fp2_en:out bit;
	  fpreg_port3_data_mux_sel: out bit;
	  convert_op : out bit_3;
	  fpreg_res_latch_en: out bit;
	  fsr_latch_en: out bit;
	  float_mux_sel: out bit_2;
	  feedback_latch_l:out bit;
	  feedback_latch_en:out bit;
	  fpdisp_out_oen:out bit;
	  fpdisp_out_len:out bit;
	  fpreg_port3_incr:out bit;
	  fpreg_port2_incr:out bit;
	  fpmult_op:out bit_2;
	  fpdiv_op:out bit_2;
	  fsr_mux_sel: out bit_2);
	  

    port map (rom_address => rom_address,
	      rom_data => rom_data,
	      fsr_out=>fsr_out,
	      phi1 => phi1, phi2 => phi2,
      	      reset => reset,
      	      opcode => instr_op,
	      opcode_ex => instr_fu,
	      ready => ready,
      	      read => read, write => write,
      	      addr_latch_en => addr_latch_en,
      	      instr_latch_en => instr_latch_en,
      	      immed_signext_en => immed_signext_en,
      	      ALU_op => ALU_op,
	      PC_out_en1 => PC_out_en1,
	      PC_out_en2 => PC_out_en2,
      	      fpreg_port1_en => fpreg_port1_en,
      	      fpreg_port2_en => fpreg_port2_en,
      	      fpreg_port3_en => fpreg_port3_en,
              fpreg_port4_en => fpreg_port4_en,
      	      reg_port1_en => reg_port1_en,
      	      reg_port2_en => reg_port2_en,
      	      reg_port3_en => reg_port3_en,
              reg_port4_en => reg_port4_en,
	      fpreg_port1_mux_sel => fpreg_port1_mux_sel,
	      fpreg_port2_mux_sel => fpreg_port2_mux_sel,
	      fpreg_port3_mux_sel => fpreg_port3_mux_sel,
	      reg_port1_mux_sel => reg_port1_mux_sel,
      	      reg_port2_mux_sel => reg_port2_mux_sel,
	      reg_port3_mux_sel => reg_port3_mux_sel,
              reg_port4_mux_sel => reg_port4_mux_sel,
	      reg_res_latch_en => reg_res_latch_en,
	      main_mux_sel => main_mux_sel,
	      datao_latch_oen=>datao_latch_oen,
	      datao_latch_len =>datao_latch_len, 
	      fpdatao_latch_oen=>fpdatao_latch_oen,
	      fpdatao_latch_len =>fpdatao_latch_len, 
	      jump => jump,
	      jump_without_add => jump_without_add,
	      PC_incr => PC_incr,
	      addr_latch_l => addr_latch_l,
	      name_signext_en => name_signext_en,
	      shift_op => shift_op,
	      shift_mux => shift_mux,
	      force_reg_31_dest => force_reg_31_dest,
	      multdiv_op =>multdiv_op,
	      fpadd_op=>fpadd_op,
	      fp2_en=>fp2_en,
	      fpreg_port3_data_mux_sel=>fpreg_port3_data_mux_sel,
	      convert_op=>convert_op,
	      fpreg_res_latch_en=>fpreg_res_latch_en,
	      fsr_latch_en=>fsr_latch_en,
	      float_mux_sel=>float_mux_sel,
	      feedback_latch_l=>feedback_latch_l,
	      feedback_latch_en=>feedback_latch_en,
	      fpdisp_out_oen=>fpdisp_out_oen,
	      fpdisp_out_len=>fpdisp_out_len,
	      fpreg_port3_incr=>fpreg_port3_incr,
	      fpreg_port2_incr=>fpreg_port2_incr,
	      fpmult_op=>fpmult_op,
	      fpdiv_op=>fpdiv_op,
	      fsr_mux_sel=>fsr_mux_sel);


  begin -- control

  -- this processor just reades the opcode for the curent state, and
  -- and outputs the control signals at the specific time that they
  -- are required as dictated by what clock cycle ther are set in,
  -- ie look below and see how some are set when phi1='1' and some
  -- are set when phi1 falls to '0'.
  state_machine: process
   
    variable state:natural;  
    variable next_state:natural :=0;

	  -- map out the control signals ont he micro rom data bus
      	  alias Aread:  bit is rom_data(0);
	  alias Awrite : bit is rom_data(1);
      	  alias Aaddr_latch_en : bit is rom_data(2);
      	  alias Ainstr_latch_en : bit is rom_data(3);
      	  alias Aimmed_signext_en : bit is rom_data(4);
      	  alias AALU_op : bit_5 is rom_data(9 downto 5);
	  alias APC_out_en1 :  bit is rom_data(10);
	  alias APC_out_en2 :  bit is rom_data(11);
      	  alias Afpreg_port1_en : bit is rom_data(12);
      	  alias Afpreg_port2_en : bit is rom_data(13);
      	  alias Afpreg_port3_en : bit is rom_data(14);
          alias Afpreg_port4_en : bit is rom_data(15);
      	  alias Areg_port1_en : bit is rom_data(16);
      	  alias Areg_port2_en : bit is rom_data(17);
      	  alias Areg_port3_en : bit is rom_data(18);
          alias Areg_port4_en : bit is rom_data(19);
	  alias Afpreg_port1_mux_sel : bit is rom_data(20);
      	  alias Afpreg_port2_mux_sel : bit is rom_data(21);
	  alias Afpreg_port3_mux_sel : bit is rom_data(22);
	  alias Areg_port1_mux_sel : bit is rom_data(23);
      	  alias Areg_port2_mux_sel : bit is rom_data(24);
      	  alias Areg_port3_mux_sel : bit is rom_data(25); 
	  alias Areg_port4_mux_sel : bit is rom_data(26);
	  alias Areg_res_latch_en : bit is rom_data(27);
	  alias Amain_mux_sel : bit_vector(2 downto 0) is rom_data(30 downto 28);
	  alias Adatao_latch_oen: bit is rom_data(31);
	  alias Adatao_latch_len : bit is rom_data(32);
	  alias Afpdatao_latch_oen: bit is rom_data(33);
	  alias Afpdatao_latch_len : bit is rom_data(34);
	  alias Ajump : bit is rom_data(35);
	  alias Ajump_without_add : bit is rom_data(36);
          alias APC_incr : bit is rom_data(37);
	  alias Aaddr_latch_l :  bit is rom_data(38);
	  alias Aname_signext_en : bit is rom_data(39);
	  alias Ashift_op : bit_2 is rom_data(41 downto 40);
	  alias Ashift_mux : bit is rom_data(42);
	  alias Aforce_reg_31_dest : bit is rom_data(43);
	  alias Abeqz : bit is rom_data(44);
	  alias Abnez : bit is rom_data(45);     
	  alias Amultdiv_op : bit_2 is rom_data(47 downto 46); 
          alias Afsr_latch_en : bit is rom_data(48);
	  alias Afpreg_port3_incr : bit is rom_data(49);
          alias Afp2_en: bit is rom_data(50);
	  alias Afpreg_port3_data_mux_sel: bit is rom_data(51);
	  alias Aconvert_op:bit_3 is rom_data(54 downto 52);
          alias Afpreg_res_latch_en:bit is rom_data(55);
	  alias Afpadd_op : bit_4 is rom_data(59 downto 56);
	  alias Afloat_mux_sel :bit_2 is rom_data(61 downto 60);
	  alias Afeedback_latch_l: bit is rom_data(62);
	  alias Afeedback_latch_en: bit is rom_data(63);
	  alias Afpdisp_out_oen: bit is rom_data(64);
	  alias Afpdisp_out_len: bit is rom_data(65);
	  alias Afpreg_port2_incr: bit is rom_data(66);
          alias Abfpt: bit is rom_data(67);
          alias Abfpf: bit is rom_data(68);
	  alias Afpmult_op: bit_2 is rom_data(70 downto 69);
	  alias Afpdiv_op: bit_2 is rom_data(72 downto 71);
	  alias Afsr_mux_sel: bit_2 is rom_data(74 downto 73);


          alias Anext_op : bit is rom_data(95);
	variable temp:bit_32;
 

  begin -- state machine

    -- set the state #
    state:=next_state;

    -- get the contol line values for this state
    natural_to_bits(state,temp);
    rom_address<=temp;
    


  ------------------------------------------------------------
    wait until phi1='1';
  ------------------------------------------------------------

        --set the control lines that need to be set in the very
	--beginning of cycle
	fsr_mux_sel<=Afsr_mux_sel;
        fpdiv_op<=Afpdiv_op;
	fpmult_op<=Afpmult_op;
	fpdisp_out_oen<=Afpdisp_out_oen;
	fpreg_port3_incr<=Afpreg_port3_incr;
	fpreg_port2_incr<=Afpreg_port2_incr;
	fp2_en<=Afp2_en;
	immed_signext_en<=Aimmed_signext_en;
	ALU_op<=AALU_op;
	multdiv_op<=Amultdiv_op;
	fpadd_op<=Afpadd_op;
	PC_out_en1<=APC_out_en1; -- full cycle, no turn off
	PC_out_en2<=APC_out_en2;
	reg_port1_en<=Areg_port1_en;
	reg_port2_en<=Areg_port2_en;
	reg_port4_en<=Areg_port4_en;
	fpreg_port1_mux_sel<=Afpreg_port1_mux_sel;
	fpreg_port2_mux_sel<=Afpreg_port2_mux_sel;
	fpreg_port3_mux_sel<=Afpreg_port3_mux_sel;
	reg_port1_mux_sel<=Areg_port1_mux_sel;
	reg_port2_mux_sel<=Areg_port2_mux_sel;
	reg_port3_mux_sel<=Areg_port3_mux_sel;
	reg_port4_mux_sel<=Areg_port4_mux_sel;
	main_mux_sel<=Amain_mux_sel;
	float_mux_sel<=Afloat_mux_sel;
	datao_latch_oen<=Adatao_latch_oen;	
	fpdatao_latch_oen<=Afpdatao_latch_oen;
	PC_incr<=APC_incr;	
	name_signext_en<=Aname_signext_en;
	jump_without_add<=Ajump_without_add;
	shift_op<=Ashift_op;
	shift_mux<=Ashift_mux;
	force_reg_31_dest<=Aforce_reg_31_dest;
        feedback_latch_l<=Afeedback_latch_l;
	addr_latch_en<=Aaddr_latch_en;
	feedback_latch_en<=Afeedback_latch_en;
	fpreg_port3_data_mux_sel<=Afpreg_port3_data_mux_sel;
	
	fpreg_res_latch_en<=Afpreg_res_latch_en;
	
	-- some lines cant be set till others settle, so wait
	wait for 15 ns; -- for logic to stabalize
	fpreg_port1_en<=Afpreg_port1_en;
	fpreg_port2_en<=Afpreg_port2_en;
	convert_op<=Aconvert_op;


	fpreg_port3_en<=Afpreg_port3_en;
	fpreg_port4_en<=Afpreg_port4_en;
	reg_port3_en<=Areg_port3_en;

	--jump if a jump instruction and condition is met
	jump<=Ajump or (Abeqz and bool_to_bit(dlatch=X"0000_0000")) or (Abnez and not bool_to_bit(dlatch=X"0000_0000")) or (Abfpt and bool_to_bit(fsr_out(12)='1')) or (Abfpf and bool_to_bit(fsr_out(12)='0'));
	write<=Awrite;

	wait for 30 ns;

  ------------------------------------------------------------
    wait until phi1='0';
  ------------------------------------------------------------
	

	reg_res_latch_en<=Areg_res_latch_en;	
	fpreg_port3_en<='0';
	fpreg_port3_incr<='0';
	fpdisp_out_oen<='0';
	write<='0';
	fpdatao_latch_oen<='0';

	--wait a bit before doing this
	wait for 10 ns; --
	read<=Aread;

	



  ------------------------------------------------------------
    wait until phi2='1';
  ------------------------------------------------------------
	fpdisp_out_len<=Afpdisp_out_len;
	addr_latch_en<='0';	
	read<='0';
	jump<='0';
	addr_latch_l<=Aaddr_latch_l; -- when pipelined, we will need to somehow make the address changeable in mid cycle to aloow for a read and a write
	datao_latch_len<=Adatao_latch_len;
	fpdatao_latch_len<=Afpdatao_latch_len;
	feedback_latch_l<='0';
	PC_incr<='0';
	instr_latch_en<=Ainstr_latch_en;	
	fsr_latch_en<=Afsr_latch_en; 

   wait for 15 ns;

	jump_without_add<='0';
   wait for 10 ns;

	addr_latch_l<='0';

   ------------------------------------------------------------
    wait until phi2='0';
  ------------------------------------------------------------

	
	fsr_mux_sel<="00";
	fpdiv_op<=b"00";
	fpmult_op<=b"00";
	fpdisp_out_len<='0';
	fp2_en<='0';
	fsr_latch_en<='0';
	fpreg_port2_incr<='0';

	feedback_latch_en<='0';
	instr_latch_en<='0';
	immed_signext_en<='0';
	ALU_op<="00000";
	multdiv_op<="00";
	fpadd_op<="0000";
	PC_out_en2<='0';
	fpreg_port1_en<='0';
	fpreg_port2_en<='0';

	fpreg_port4_en<='0';
	reg_port1_en<='0';
	reg_port2_en<='0';
	reg_port3_en<='0';
	reg_port4_en<='0';
	fpreg_port1_mux_sel<='0';
	fpreg_port2_mux_sel<='0';
	fpreg_port3_mux_sel<='0';
	reg_port1_mux_sel<='0';
	reg_port2_mux_sel<='0';
	reg_port3_mux_sel<='0';
	reg_port4_mux_sel<='0';
	reg_res_latch_en<='0';
	main_mux_sel<="000";
	float_mux_sel<="00";
	datao_latch_oen<='0';
	datao_latch_len<='0';

	fpdatao_latch_len<='0';

	name_signext_en<='0';
	shift_op<="00";
	shift_mux<='0';
	force_reg_31_dest<='0';
	fpreg_port3_data_mux_sel<='0';
	convert_op<="000";
	fpreg_res_latch_en<='0';


	-- calculate next state
	-- if we are at the end of an instruction (ie
        -- bit 94 is set in this states microcode rom)
        -- start at state 1
        -- if we are at state 2 then use opcode to determine new location.


	if(state=2) then

	case opcode is
          when "000000" =>
	    next_state:=bits_to_uint(bits_or(opcode_ex, "1000000"))*8;
	  
	  when "000001" => 
	    next_state:=bits_to_uint(bits_or(opcode_ex, "10000000"))*8;
	  
	  when others =>
	 
	    next_state:=bits_to_uint(opcode)*8;
	  end case;

	else
	  next_state:=state+1;
	end if;

	if (Anext_op = '1' ) then
	  next_state :=1;
	end if;

  end process state_machine;


  end block control;


  end block controller;
  
end RTL;