dp32_rtl.vhd

DLX CPU VHDL CODE UNIVERSITY

  port map (phi1=>phi1, phi2 =>phi2, 
	operand1=>op1_bus,
      	operand2=>op2_bus,
	result =>mm1,
	command=>multdiv_op);


-- covert between fp, dpfp, and ints
  FP_Converter : convert
  port map ( Fin=>op1_bus, Din=>op1b_bus,
	 Fout=>mm5, Dout=>fm0,
	 Op =>convert_op
         );

-- the mux that chooses between the various units for writeback
  main_mux : mux8
    generic map (width => 32)
    port map (i0 => mm0, i1 => mm1, i2 => d_bus, i3 => mm3,
              i4 => mm4, i5 => mm5, i6 => mm6, i7 => mm7,
              y => r_bus,
	      sel => main_mux_sel);
 
-- selecter for the fp writeback
  float_mux : mux4
    generic map (width => 32)
    port map (i0 => fm0, i1 => fm1, i2 => fm2, i3 => fm3,
                     y => fpr_bus,  sel => float_mux_sel);

-- chooses which fsr to write back, each fp unit creates an fsr value
  fsr_mux : mux4
    generic map (width => 32)
    port map (i0 => fsr_0, i1 => fsr_1, i2 => fsr_2, i3 => op1_bus,
                     y => fsr_in,  sel => fsr_mux_sel);


  --not in use now
  fpreg_port3_data_mux : mux2
    generic map (width => 32)
    port map (i0 => reg_result, i1 => fpdisp_line, y => fpreg_d3,
	      sel => fpreg_port3_data_mux_sel);  

-- register muxes follow
  fpreg_port1_mux : mux2
    generic map (width => 5)
    port map (i0 => instr_r1, i1 => instr_r2, y => fpreg_a1,
	      sel => fpreg_port1_mux_sel);

  fpreg_port2_mux : mux2
    generic map (width => 5)
    port map (i0 => instr_r1, i1 => instr_r2, y => fpreg_a2,
	      sel => fpreg_port2_mux_sel);

  reg_port1_mux : mux2
    generic map (width => 5)
    port map (i0 => instr_r1, i1 => instr_r2, y => reg_a1,
	      sel => reg_port1_mux_sel);

  reg_port2_mux : mux2
    generic map (width => 5)
    port map (i0 => instr_r1, i1 => instr_r2, y => reg_a2,
	      sel => reg_port2_mux_sel);

  reg_port3_mux : mux2
    generic map (width => 5)
    port map (i0 => reg_a3b, i1 => instr_r3, y => reg_a3,
	      sel => reg_port3_mux_sel);

  reg_port3b_mux : mux2
    generic map (width => 5)
    port map (i0 => instr_r2, i1 => value_31, y => reg_a3b,
	      sel => force_reg_31_dest);

-- choose value to use as the shift amount
  shifter_mux : mux2
    generic map (width => 5)
    port map (i0 => instr_si, i1 => op2_bus(4 downto 0), y => shift_amount,
	      sel => shift_mux);

  reg_port4_mux : mux2
    generic map (width => 5)
    port map (i0 => instr_r1, i1 => instr_r2, y => reg_a4,
	      sel => reg_port4_mux_sel);

  fpreg_port3_mux : mux2
    generic map (width => 5)
    port map (i0 => instr_r2, i1 => instr_r3, y => fpreg_a3,
	      sel => fpreg_port3_mux_sel);


  fsr_latch : latch
    generic map (width => 32)
    port map (d => fsr_in, q => fsr_val, en => fsr_latch_en);

-- the writeback latch
  reg_res_latch : latch
    generic map (width => 32)
    port map (d => r_bus, q => reg_result, en => reg_res_latch_en);

--fp writeback latch
  fpreg_res_latch : latch
    generic map (width => 32)
    port map (d => fpr_bus, q => fpreg_result, en => fpreg_res_latch_en);
  
-- fp adder
  fpadd : fau  
    port map  ( phi1=>phi1, phi2=>phi2,
	    Op1=>op1_bus,Op1b=>op1b_bus,
	    Op2=>op2_bus,Op2b=>op2b_bus, 
	    R=>mm4, Rb=>fm1,
	    fsr_in=>fsr_val,
	    fsr_out=>fsr_0,
	    operation=>fpadd_op);


-- fp multiplyer
  fpmult : fmu  
    port map ( phi1=>phi1,phi2=>phi2,  
	  Op1=>op1_bus,Op1b=>Op1b_bus,Op2=>Op2_bus,Op2b=>Op2b_bus,
	  R1=>mm6, R2=>fm2,
	  operation =>fpmult_op,
	  fsr_in=>fsr_val,
	  fsr_out=>fsr_1);

-- fp divider
  fpdiv : fp_div 
  port map( phi1=>phi1, phi2=>phi2,
	Op1=>op1_bus, Op1b=>Op1b_bus, Op2=>Op2_bus, Op2b=>Op2b_bus,
	R=>mm7, Rb=>fm3,
	op=>fpdiv_op,
	fsr_in=>fsr_val,
	fsr_out=>fsr_2);


-- instruction fetch unit
  IFUnit : IF_Unit
    port map (d=> r_bus,
          q1 =>a_bus,
	  q2 =>op1_bus,
	  j =>jump,
          jwa => jump_without_add,
          oe1 => PC_out_en1,
          oe2 => PC_out_en2,
	  reset =>reset,
          PC_incr => PC_incr,
          phi1 =>phi1,
	  phi2 =>phi2);

-- the alu 
  ALU : ALU_32
    port map (operand1 => op1_bus, operand2 => op2_bus,
	      result => mm0, cond_code => ALU_CC,
	      command => ALU_op);

-- the b arrel shifter
  Shift : shifter 
     port map (operand => op1_bus,
          result => mm3,
	  amount => shift_amount,
	  command =>shift_op);

-- the upper 32 bits of the fr writeback register
    fp2_buffer : buffer_32
    port map (a => fp2, b => op2_bus,
	      en => fp2_en);
  
  fpdisp_latch : latch_buffer_32
    port map (d => d_bus, q => fpdisp_line,
      	      latch_en => fpdisp_out_len, out_en => fpdisp_out_oen);

  datao_latch : latch_buffer_32
    port map (d => dlatch, q => d_bus, --d=dp2?
      	      latch_en => datao_latch_len, out_en => datao_latch_oen);

  fpdatao_latch : latch_buffer_32
    port map (d => fp2, q => d_bus,
      	      latch_en => fpdatao_latch_len, out_en => fpdatao_latch_oen);

  addr_latch : latch_buffer_32
    port map (d => r_bus, q => a_bus,
	      latch_en => addr_latch_l, out_en => addr_latch_en);

  feedback_latch : latch_buffer_32
    port map (d => r_bus, q => op1_bus,
	      latch_en => feedback_latch_l, out_en => feedback_latch_en);

  instr_latch : latch
    generic map (width => 32)
    port map (d => d_bus, q => current_instr,
	      en => instr_latch_en);

  immed_signext : signext_16_32
    port map (a => instr_im, b => op2_bus,
	      en => immed_signext_en);

  name_signext : signext_26_32
    port map (a => instr_na, b => op2_bus ,
	      en => name_signext_en);
  




--******************** MAIN PART OF CONTROL LOGIC *******************

  controller : block

    port (fsr_out : in bit_vector;
	  phi1, phi2 : in bit;
      	  reset : in bit;
      	  opcode : in bit_6;
          opcode_ex : in bit_6;
      	  read, write : out bit;
          ready : in bit;
      	  addr_latch_en : out bit;
      	  instr_latch_en : out bit;
      	  immed_signext_en : out bit;
      	  ALU_op : out bit_5;
	  PC_out_en1 : out bit;
	  PC_out_en2 : out bit;
      	  fpreg_port1_en : out bit;
      	  fpreg_port2_en : out bit;
      	  fpreg_port3_en : out bit;
          fpreg_port4_en : out bit;
      	  reg_port1_en : out bit;
      	  reg_port2_en : out bit;
      	  reg_port3_en : out bit;
          reg_port4_en : out bit;
	  fpreg_port1_mux_sel : out bit;
      	  fpreg_port2_mux_sel : out bit;
	  fpreg_port3_mux_sel : out bit;
	  reg_port1_mux_sel : out bit;
      	  reg_port2_mux_sel : out bit;
      	  reg_port3_mux_sel : out bit;
	  reg_port4_mux_sel : out bit;
	  reg_res_latch_en : out bit;
	  main_mux_sel : out bit_vector(2 downto 0);
	  datao_latch_oen, datao_latch_len : out bit;
	  fpdatao_latch_oen, fpdatao_latch_len : out bit;
	  jump,jump_without_add : out bit;
          PC_incr : out bit;
	  addr_latch_l : out bit;
	  name_signext_en : out bit;
	  shift_op : out bit_2;
	  shift_mux : out bit;
	  force_reg_31_dest : out bit;
	  multdiv_op : out bit_2;
	  fpadd_op : out bit_4;
	  fp2_en : out bit;
	  fpreg_port3_data_mux_sel : out bit;
	  convert_op : out bit_3;
	  fpreg_res_latch_en: out bit;
	  fsr_latch_en: out bit;
	  float_mux_sel: out bit_2;
	  feedback_latch_l:out bit;
	  feedback_latch_en:out bit;
	  fpdisp_out_oen: out bit;
	  fpdisp_out_len: out bit;
	  fpreg_port3_incr: out bit;
	  fpreg_port2_incr: out bit;
	  fpmult_op: out bit_2;
	  fpdiv_op: out bit_2;
          fsr_mux_sel: out bit_2);

    port map (fsr_out=>fsr_val,
	      phi1 => phi1, phi2 => phi2,
      	      reset => reset,
      	      opcode => instr_op,
	      opcode_ex => instr_fu,
      	      read => read, write => write,
	      ready => ready,
      	      addr_latch_en => addr_latch_en,
      	      instr_latch_en => instr_latch_en,
      	      immed_signext_en => immed_signext_en,
      	      ALU_op => ALU_op,
	      PC_out_en1 => PC_out_en1,
	      PC_out_en2 => PC_out_en2,
      	      fpreg_port1_en => fpreg_port1_en,
      	      fpreg_port2_en => fpreg_port2_en,
      	      fpreg_port3_en => fpreg_port3_en,
              fpreg_port4_en => fpreg_port4_en,
      	      reg_port1_en => reg_port1_en,
      	      reg_port2_en => reg_port2_en,
      	      reg_port3_en => reg_port3_en,
              reg_port4_en => reg_port4_en,
	      fpreg_port1_mux_sel => fpreg_port1_mux_sel,
	      fpreg_port2_mux_sel => fpreg_port2_mux_sel,
	      fpreg_port3_mux_sel => fpreg_port3_mux_sel,
	      reg_port1_mux_sel => reg_port1_mux_sel,
      	      reg_port2_mux_sel => reg_port2_mux_sel,
	      reg_port3_mux_sel => reg_port3_mux_sel,
              reg_port4_mux_sel => reg_port4_mux_sel,
	      reg_res_latch_en => reg_res_latch_en,
	      main_mux_sel => main_mux_sel,
	      datao_latch_oen=>datao_latch_oen,
	      datao_latch_len =>datao_latch_len, 
	      fpdatao_latch_oen=>fpdatao_latch_oen,
	      fpdatao_latch_len =>fpdatao_latch_len, 
	      jump => jump,
	      jump_without_add => jump_without_add,
	      PC_incr => PC_incr,
	      addr_latch_l => addr_latch_l,
	      name_signext_en => name_signext_en,
	      shift_op => shift_op,
	      shift_mux => shift_mux,
	      force_reg_31_dest => force_reg_31_dest,
	      multdiv_op=>multdiv_op,
	      fpadd_op=>fpadd_op,
	      fp2_en=>fp2_en,
	      fpreg_port3_data_mux_sel=>fpreg_port3_data_mux_sel,
	      convert_op=>convert_op,
	      fpreg_res_latch_en=>fpreg_res_latch_en,
	      fsr_latch_en=>fsr_latch_en,
	      float_mux_sel=>float_mux_sel,
	      feedback_latch_l=>feedback_latch_l,
	      feedback_latch_en=>feedback_latch_en,
	      fpdisp_out_oen=>fpdisp_out_oen,
	      fpdisp_out_len=>fpdisp_out_len,
	      fpreg_port3_incr=>fpreg_port3_incr,
	      fpreg_port2_incr=>fpreg_port2_incr,
	      fpmult_op=>fpmult_op,
	      fpdiv_op=>fpdiv_op,
	      fsr_mux_sel=>fsr_mux_sel);

  component microrom 
  generic ( Tac_read : Time := 4 ns;
            load_file_name : string := "microcode.txt" );
  port ( a : in bus_bit_32 bus;
	 d : out bit_96
         );
  end component;

  -- signals needed for micro rom
  signal rom_address : bit_32;
  signal rom_data    : bit_96;

  begin  -- block controller


  rom : microrom
    port map (a => rom_address, d => rom_data);

  control : block

    port (rom_address : out bit_32;
          rom_data : in bit_96;
	  fsr_out : in bit_vector;
          phi1, phi2 : in bit;
      	  reset : in bit;
      	  opcode : in bit_6;
          opcode_ex : in bit_6;
          ready : in bit;
      	  read, write : out bit;
      	  addr_latch_en : out bit;
      	  instr_latch_en : out bit;
      	  immed_signext_en : out bit;
      	  ALU_op : out bit_5;
	  PC_out_en1 : out bit;
	  PC_out_en2 : out bit;
      	  fpreg_port1_en : out bit;
      	  fpreg_port2_en : out bit;
      	  fpreg_port3_en : out bit;
          fpreg_port4_en : out bit;
      	  reg_port1_en : out bit;
      	  reg_port2_en : out bit;
      	  reg_port3_en : out bit;
          reg_port4_en : out bit;
	  fpreg_port1_mux_sel : out bit;
      	  fpreg_port2_mux_sel : out bit;
	  fpreg_port3_mux_sel : out bit;
	  reg_port1_mux_sel : out bit;
      	  reg_port2_mux_sel : out bit;
      	  reg_port3_mux_sel : out bit;
	  reg_port4_mux_sel : out bit;
	  reg_res_latch_en : out bit;
	  main_mux_sel : out bit_vector(2 downto 0);
	  datao_latch_oen, datao_latch_len : out bit;
	  fpdatao_latch_oen, fpdatao_latch_len : out bit;
	  jump,jump_without_add : out bit;
          PC_incr : out bit;