dp32_rtl.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all, work.ALU_32_types.all, work.fpadd_pkg.all;


architecture RTL of dp32 is


  -- floating point register file
  component reg_file_32_rrwr
    generic (depth : positive);
    port (a1 : in bit_vector(depth-1 downto 0);
  	  q1 : out bus_bit_32 bus;
	  en1 : in bit;
	  a2 : in bit_vector(depth-1 downto 0);
	  q2 : out bus_bit_32 bus;
	  en2 : in bit;
	  a3 : in bit_vector(depth-1 downto 0);
	  d3 : in bit_32;
	  en3 : in bit;
	  a4 : in bit_vector(depth-1 downto 0);
	  q4 : out bus_bit_32 bus;
	  en4 : in bit);
  end component;


  --register file for normal registers
  component reg_file_32_rrww
    generic (depth : positive);
    port (a1 : in bit_vector(depth-1 downto 0);
  	  q1 : out bus_bit_32 bus;
	  en1 : in bit;
	  q1b: out bus_bit_32 bus;
	  a2 : in bit_vector(depth-1 downto 0);
	  q2 : out bus_bit_32 bus;
	  en2 : in bit;
	  q2b: out bus_bit_32 bus;
          incr2 : in bit;
	  a3 : in bit_vector(depth-1 downto 0);
	  d3 : in bit_32;
	  en3 : in bit;
	  incr3 : in bit;
	  a4 : in bit_vector(depth-1 downto 0);
	  d4 : in bit_32;
	  en4 : in bit;
	  d4b : in bit_32);

  end component;

  -- the multiplyer and divider unit for the cpu
  component multdiv 
  generic (Tpd : Time := unit_delay);
  port (phi1, phi2 : in bit;
	operand1 : in bit_32;
      	operand2 : in bit_32;
	result : out bus_bit_32 bus;
	command : in bit_2);
  end component;

  -- the divider
  component fp_div 
  generic( simulation_delay : time := 10 ns );
  port( phi1,phi2 : in bit;
	Op1, Op1b, Op2, Op2b : in bit_32;
	R, Rb : inout bit_32;
	op : in bit_2;
	fsr_in: in bit_32;
	fsr_out : out bit_32 );
  end component;


  -- fp adder, subtractor, comparer
  component fau  
    port  ( phi1, phi2 : in bit;
	    Op1,Op1b, Op2, Op2b : in bit_vector(31 downto 0);
	    R, Rb : out bit_vector (31 downto 0);
	    fsr_in : in bit_32;
	    fsr_out : out bit_32;
	    operation : in bit_4);  
  end component;
  
  -- fp multiplyer
  component fmu  
    port ( phi1,phi2  : in bit;
	  Op1,Op1b,Op2,Op2b: in bit_32;
	  R1,R2	: out bit_32;
	  operation : in bit_2;
	  fsr_in:  in bit_32;
	  fsr_out : out bit_32);
  end component;

  -- a 2 input mux, variable width
  component mux2
    generic (width : positive);
    port (i0, i1 : in bit_vector(width-1 downto 0);
      	  y : out bit_vector(width-1 downto 0);
	  sel : in bit);
  end component;

  --4 input mux with variable width
  component mux4
    generic (width : positive);
    port (i0, i1, i2, i3 : in bit_vector(width-1 downto 0);
      	  y : out bit_vector(width-1 downto 0);
	  sel : in bit_2);
  end component;

  --8 input mux with variable width
  component mux8
    generic (width : positive);
    port (i0, i1, i2, i3, i4, i5, i6, i7: in bit_vector(width-1 downto 0);
      	  y : out bit_vector(width-1 downto 0);
	  sel : in bit_vector (2 downto 0));
  end component;

  -- storage area of micro code
  component microrom 
  generic ( Tac_read : Time := 4 ns;
            load_file_name : string := "microcode.txt" );
  port ( a : in bus_bit_32 bus;
	 d : out bit_96
         );
  end component;

  --instruction fetch unit
  component IF_Unit
    port (d : in bit_32;
          q1, q2 : out bus_bit_32 bus;
	  j,jwa : in bit;
          oe1,oe2: in bit;
          reset : in bit;
          PC_incr : in bit;
          phi1, phi2 : in bit
    );
    end component;

  --barrle shifter
  component shifter 
   port (operand : in bit_32;
        result : out bus_bit_32 bus;
	amount : in bit_5;
	command : in bit_2);
  end component;


  -- alu that does add, sub, and various lovical operations
  component ALU_32
    port (operand1 : in bit_32;
      	  operand2 : in bit_32;
	  result : out bus_bit_32 bus;
	  cond_code : out CC_bits;
	  command : in bit_5);
  end component;
  
  -- a buffer
  component buffer_32
    port (a : in bit_32;
      	  b : out bus_bit_32 bus;
	  en : in bit);
  end component;

  -- fp single, fp double and integer format converter
  component convert 
  port ( Fin, Din : in bit_32;
	 Fout, Dout : out bit_32;
	 Op : in bit_3
         );
  end component;
  
  --a variable width register(latch)
  component latch
    generic (width : positive);
    port (d : in bit_vector(width-1 downto 0);
      	  q : out bit_vector(width-1 downto 0);
	  en : in bit);
  end component;
  
  -- a variabe width register with output control
  component latch_buffer_32
    port (d : in bit_32;
      	  q : out bus_bit_32 bus;
	  latch_en : in bit;
	  out_en : in bit);
  end component;

  --sign extend a 16 bit to a 32 bit #
  component signext_16_32
    port (a : in bit_16;
      	  b : out bus_bit_32 bus;
	  en : in bit);
  end component;

  --sign extend a 26 bit # to a 32 bit one
  component signext_26_32
    port (a : in bit_26;
      	  b : out bus_bit_32 bus;
	  en : in bit);
  end component;


--*********************** SIGNALS *********************
  
  --outpuuts of register files 1 and 2
  signal op1_bus : bus_bit_32;
  signal op2_bus : bus_bit_32;

  --latched output of main_mux
  signal r_bus : bus_bit_32;
  
  -- current instruction
  signal current_instr : bit_32;

  --the parts of the instruction tat are useful, ie operands, opcode, ect
  alias instr_r1 : bit_vector(4 downto 0) is current_instr(25 downto 21);
  alias instr_r2 : bit_vector(4 downto 0) is current_instr(20 downto 16);
  alias instr_r3 : bit_vector(4 downto 0) is current_instr(15 downto 11);
  alias instr_op : bit_vector(5 downto 0) is current_instr(31 downto 26);
  alias instr_im : bit_vector(15 downto 0) is current_instr(15 downto 0);
  alias instr_fu : bit_vector(5 downto 0 ) is current_instr(5 downto 0);
  alias instr_na : bit_vector(25 downto 0) is current_instr(25 downto 0);
  alias instr_si : bit_vector(4 downto 0) is current_instr(4 downto 0);
  
  -- 4 signals the float_mux can choose between and the select lines
  signal fm0, fm1,fm2,fm3 : bit_32;
  signal float_mux_sel : bit_2;
  
  -- register address lines
  signal reg_a1, reg_a2, reg_a3, reg_a3b, reg_a4 : bit_5;
  signal fpreg_a1, fpreg_a2, fpreg_a3, fpreg_a3b, fpreg_a4 : bit_5;
  
  --control over data latched onto main memory data bus
  signal datao_latch_oen, datao_latch_len: bit;  
  signal fpdatao_latch_oen, fpdatao_latch_len: bit;  

  --resgister file stuff
  signal reg_port1_en : bit;
  signal reg_port2_en : bit;
  signal reg_port3_en : bit;
  signal reg_port4_en : bit;
  signal reg_port1_mux_sel : bit;
  signal reg_port2_mux_sel : bit;
  signal reg_port4_mux_sel : bit;
  signal reg_port3_mux_sel : bit;

  -- force the store to goto register #31
  signal force_reg_31_dest: bit;


  --fp reg file stuff
  signal fpreg_port1_en : bit;
  signal fpreg_port2_en : bit;
  signal fpreg_port3_en : bit;
  signal fpreg_port4_en : bit;
  signal fpreg_port3_mux_sel : bit;
  signal fpreg_port1_mux_sel : bit;
  signal fpreg_port2_mux_sel : bit;
  signal fpreg_port3_incr : bit;  
  signal fpreg_port2_incr : bit;  
  signal fpreg_port3_data_mux_sel : bit;

  -- signals for the main mux
  signal mm0,mm1,mm2,mm3,mm4,mm5,mm6,mm7: bit_32;
  signal main_mux_sel : bit_3;

  --to tell alu what to do
  signal ALU_op : bit_5;

  --latch data bus into current instruction register
  signal instr_latch_en : bit;

  --tell the IF unit to jump
  signal jump,jump_without_add : bit;

  -- tell if unit to increment the memory pointer
  signal PC_incr : bit;

  -- latch the pc value, ie jump
  signal PC_latch_en : bit;

  -- lines to store fsr from fp operations
  signal fsr_0, fsr_1, fsr_2: bit_32;
  signal fsr_in, fsr_val : bit_32;
  signal fsr_mux_sel : bit_2;

  -- latch the fsr
  signal fsr_latch_en : bit;

  --control ofer barrl shifer related stuff
  signal shift_amount : bit_5;
  signal shift_op: bit_2;
  signal shift_mux: bit;

  --sign extend the name part of the operand to 32 bits
  signal name_signext_en : bit;

  --multiplyer and divisor operand
  signal multdiv_op: bit_2;

  --condition codes - not used
  signal ALU_CC : CC_bits;
  signal CC : CC_bits;
  signal CC_latch_en : bit;
  signal CC_comp_result : bit;

  -- output and control for the fpreg_res_latch
  signal fpreg_result : bit_32;
  signal fpreg_res_latch_en : bit;

  -- reg_res_latch stuff
  signal reg_result : bit_32;
  signal reg_res_latch_en : bit;

  -- sign extend the 16 bit immediat value to 32 bit
  signal immed_signext_en : bit;

  -- control of the 2 pc output ports on the IF unit
  signal PC_out_en1 : bit;
  signal PC_out_en2 : bit;

  -- input, output and control of the fp_converter
  signal convert_i1, convert_i2, convert_o1, convert_o2: bit_32;
  signal convert_op : bit_3;

  -- fp division control
  signal fpdiv_op : bit_2;

  --some lines that go nowhere but are needed anyway
  signal null4 : bit_32;
  signal nowhere_32 : bit_32;

  --fp multiplyer operand
  signal fpmult_op : bit_2;

  --misclaneous others
  signal fpreg_d3 : bit_32;
  signal addr_latch_en : bit;
  signal disp_latch_en : bit;
  signal disp_out_en : bit;
  signal d2_en : bit;
  signal dr_en : bit;
  signal fpreg_result1, fpreg_result2 : bit_32;
  signal op1b_bus, op2b_bus : bit_32;
  signal fpd1,fpd2 : bit_32;
  signal feedback_latch_l,feedback_latch_en:bit;
  signal addr_latch_l : bit;
  signal dlatch : bit_32;
  signal instr_cm : bit_4;
  signal value_31 : bit_5 :="11111";
  signal fpadd_op : bit_4;
  signal fp2 : bit_32;
  signal fp2_en : bit;
  signal fpr_bus : bit_32;
  signal fpdisp_line: bit_32;
  signal fpdisp_out_oen, fpdisp_out_len : bit;

  


begin -- architecture RTL of dp32


-- the main register bank
  reg_file : reg_file_32_RRWR
    generic map (depth => 5)
    port map (a1 => reg_a1, q1 => op1_bus, en1 => reg_port1_en,
	      a2 => reg_a2, q2 => op2_bus, en2 => reg_port2_en,
	      a3 => reg_a3, d3 => reg_result, en3 => reg_port3_en,
	      a4 => reg_a4, q4=> dlatch, en4 => reg_port4_en);

-- the fp registers
  fpreg_file : reg_file_32_RRWW
    generic map (depth => 5)
    port map (a1 => fpreg_a1, q1 => op1_bus, en1 => fpreg_port1_en,
	      q1b => op1b_bus, 
	      a2 => fpreg_a2, q2 => fp2, en2 => fpreg_port2_en,
	      q2b => op2b_bus,	incr2=>fpreg_port2_incr,
	      a3 => fpreg_a3, d3 => fpreg_d3, en3 => fpreg_port3_en, incr3=>fpreg_port3_incr,
	      a4 => instr_r3, d4 =>  reg_result, en4 => fpreg_port4_en, d4b=>fpreg_result );
	  
-- the multiplyer and divider unit
  multdiv_unit : multdiv