create_flags.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;


entity create_flags is
    port (nan, z, v,u,n: in bit;
	  flags : out bit_5);
end create_flags;


architecture behaviour of create_flags is
begin

main : process (nan,z,v,u,n)

begin
flags<="00000";
flags(4)<=nan;
flags(3)<=z;
flags(2)<=v;
flags(1)<=u;
flags(0)<=n;

end process;



end behaviour;