reg_file_32_rrww.vhd

DLX CPU VHDL CODE UNIVERSITY

--
-- $RCSfile: reg_file_32_rrw.vhd,v $
-- $Revision: 1.1 $
-- $Author: petera $
-- $Date: 90/06/21 10:02:59 $
--

use work.dp32_types.all;

entity reg_file_32_rrww is
  generic (depth : positive;		  -- number of address bits
      	    Tpd : Time := unit_delay;
      	    Tac : Time := unit_delay);
  port (a1 : in bit_vector(depth-1 downto 0);
  	q1 : out bus_bit_32 bus;
	en1 : in bit;
	q1b: out bus_bit_32 bus;
	a2 : in bit_vector(depth-1 downto 0);
	q2 : out bus_bit_32 bus;
	en2 : in bit;
	q2b: out bus_bit_32 bus;
	incr2 : in bit;
	a3 : in bit_vector(depth-1 downto 0);
	d3 : in bit_32;
	en3 : in bit;
	incr3 :in bit;
	a4 : in bit_vector(depth-1 downto 0);
	d4 : in bit_32;
	en4 : in bit;
	d4b : in bit_32);

end reg_file_32_rrww;

architecture behaviour of reg_file_32_rrww is
  
begin

  reg_file: process (a1, en1, a2, en2, a3, d3, en3,a4,en4)

    subtype reg_addr is natural range 0 to (power(2,(depth-1))+1);
    type register_array is array (reg_addr) of bit_32;
    
    variable registers : register_array;

  begin
    if en3 = '1' then
--       	    ASSERT false REPORT "fpreg port 3 write to: " SEVERITY warning;
  --     	    ASSERT false REPORT vector_to_string(a3) SEVERITY warning;
	if (incr3='0') then
	      registers(bits_to_natural(a3)) := d3;
	else
	      registers(bits_to_natural(a3)+1):=d3;
	end if;	

    end if;
    if en4 = '1' then
      -- 	    ASSERT false REPORT "fpreg port 4 write to:"  SEVERITY warning;
    --   	    ASSERT false REPORT vector_to_string(a4) SEVERITY warning;
      registers(bits_to_natural(a3)) := d4;
      registers(bits_to_natural(a3)+1) := d4b;
    end if;
    if en1 = '1' then
      q1 <= registers(bits_to_natural(a1)) after Tac;
      q1b <= registers(bits_to_natural(a1)+1) after Tac;
    else
      q1 <= null after Tpd;
    end if;
    if en2 = '1' then
	if incr2='0' then
	      q2 <= registers(bits_to_natural(a2)) after Tac;
	      q2b <= registers(bits_to_natural(a2)+1) after Tac;
        else
	      q2 <= registers(bits_to_natural(a2)+1) after Tac;
	      q2b <= registers(bits_to_natural(a2)+2) after Tac;
        end if;
    else
      q2 <= null after Tpd;
    end if;
 
    registers(0):=X"0000_0000";	 
  end process reg_file;

end behaviour;