convert.vhd

DLX CPU VHDL CODE UNIVERSITY

library IEEE;
use STD.textio.all;
use IEEE.std_logic_1164.all;
use work.dp32_types.all;



entity convert is
  port ( Fin, Din : in bit_32;
	 Fout, Dout : out bit_32;
	 Op : in bit_3
         );

end convert;

architecture procedureal of convert is




    constant F2D :  bit_3 := "000";
    constant F2I :  bit_3 := "001";
    constant D2F :  bit_3 := "010";
    constant D2I :  bit_3 := "011";
    constant I2F :  bit_3 := "100";
    constant I2D :  bit_3 := "101";
    constant D2D :  bit_3 := "110";


  procedure FS2D (i   : in bit_32   ; o1, o2 : out bit_32) is
  
  variable V : bit_64:=X"0000000000000000";
  alias H : bit_32 is V(63 downto 32); 
  alias L : bit_32 is V(31 downto 0); 
  alias Oexp : bit_8 is i(30 downto 23);
  alias Nexp : bit_11 is V(62 downto 52); 
  alias Omant : bit_23 is i(22 downto 0);
  alias Nmant : bit_23 is V(51 downto 29);

  begin
 
  V(63):=i(31); --copy sign bit
  int_to_bits(bits_to_uint(Oexp)+896,Nexp); --create new exponent
  Nmant:=Omant; -- copy mantissa
  o1:=L;
  o2:=H;

  end FS2D;






  procedure FI2D (i   : in bit_32   ; o1, o2 : out bit_32) is
    variable r: bit_64;
    alias rl: bit_32 is r(31 downto 0);
    alias rh: bit_32 is r(63 downto 32);
    alias rs: bit is r(63);
    alias re: bit_11 is r(62 downto 52);
    alias rm: bit_52 is r(51 downto 0);
    variable l,t: integer:=0;
    variable i2: bit_32;
    
  begin
    rm:=X"0000000000000";
    if(i(31)='1') then
      rs:='1';
      i2:=twos_complement(i);
    else
      rs:='0';
      i2:=i;
    end if;   
 
    for u in i'range loop
      if(i2(u)='1' and t=0) then
      --i2(u):='0';	
      t:=u;
      end if;
    end loop;
	
    int_to_bits((t)+1023,re);	

--    if(t>51) then
  --    l:=0;
   -- else
     -- l:=t-51; --*******************************

      rm(51 downto (52-t)):=i2((t-1) downto 0);
   -- end if;
    o1:=rl;
    o2:=rh;


  end FI2D;










  procedure FD2S (i1,i2   : in bit_32   ; o1 : out bit_32) is

    variable inn: bit_64;
    alias iss: bit is inn(63);
    alias ie: bit_11 is inn(62 downto 52);
    alias im: bit_52 is inn(51 downto 0);
    alias os: bit is o1(31);
    alias oe: bit_8 is o1(30 downto 23);
    alias om: bit_23 is o1(22 downto 0);
    variable e: integer;
 begin
    inn:=i2&i1;
    os:=iss;
    e:=bits_to_uint(ie)-127;
    int_to_bits(e+1023,oe);
    
    om:=im(51 downto 29); 
 

  end FD2S;





  procedure FD2I (i1,i2   : in bit_32   ; o1: out bit_32) is
    --variable tbv,tbc : bit_vector;
    variable r: bit_32;
    variable inn:bit_64;
    alias s: bit is inn(63);
    alias e: bit_11 is inn(62 downto 52);
    alias m: bit_52 is inn(51 downto 0);
    variable h,ei: integer;
  begin
    inn:=i2&i1;
    ei:=bits_to_uint(e);
    ei:=ei-1023;
    r((ei-1) downto 0):=m(51 downto (52-ei));
    r(ei):='1';
-- ******* currewntly rounds down, make to round closest
--    if(m(51-ei)='1')then
  --    h=bits_to_uint(
--    end if;
    if(s='1') then
	o1:=twos_complement(r);
    else   
	o1:=r;
    end if;



  end FD2I;

  begin






  convert_behavior : process 


  variable t1,t2,t3 : bit_32;

  begin
  --assert false report "convert" severity warning;
  wait for 1 ns;
  case  Op is
	when D2I =>
	FD2I(Fin,Din,t1);
	Fout<=t1;	
        Dout<=X"00000000";

	when D2F =>
	FD2S(Fin,Din,t1);
	Fout<=t1;	
        Dout<=X"00000000";

	when F2I =>
	FS2D(Fin,t1,t2);
	FD2I(t1,t2,t1);
	Fout<=t1;	
        Dout<=X"00000000";

	when F2D =>
	FS2D(Fin,t1,t2);
	Fout<=t1;
	Dout<=t2;

	when I2F =>
	FI2D(Fin,t1,t2);
	FD2S(t1,t2,t3);
	Fout<=t3;
        Dout<=X"00000000";

	when I2D =>
	FI2D(Fin,t1,t2);
	Fout<=t1;
	Dout<=t2;
	
	when D2D=>
	Fout<=Fin;
	Dout<=Din;

	
	when others=>

  end case;

     
  end process convert_behavior;

end procedureal;