mant_ext.vhd

DLX CPU VHDL CODE UNIVERSITY

library IEEE;
use STD.textio.all;
use IEEE.std_logic_1164.all;
use work.dp32_types.all;



entity mant_ext is
    generic(width: positive);
    port(a :in bit_vector(width-1 downto 0);
         y: out bit_vector(width-1 downto 0));
end mant_ext;



architecture behaviour of mant_ext is


begin
main : process(a)
begin
	--wait for 1 ns;

	y<=a;
	y(width-1)<='1';

end process;
end behaviour;






entity mant_cut is
    generic(width: positive);
    port(a :in bit_vector(width-1 downto 0);
         y: out bit_vector(width-5 downto 0));
end mant_cut;



architecture behaviour of mant_cut is


begin
main : process (a)
begin

--wait for 1 ns;
y<=a(width-2 downto 3);

end process;
end behaviour;