adder_signed.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;



entity adder_signed is
    generic(width : positive);
    port(a,b : in bit_vector(width-1 downto 0);
         y : out bit_vector(width-1 downto 0);
	 o : out bit );
end adder_signed;

architecture behaviour of adder_signed is


begin

main : process (a,b)

variable t: bit_vector(width-1 downto 0);
begin
--wait for 1 ns;



if(bits_to_int(a)+bits_to_int(b) > power(2,width)-1)then
  o<='1';
else
  o<='0';
  int_to_bits(bits_to_int(a)+bits_to_int(b) ,t);
  y<=t;
end if;


end process;
end behaviour;