reg_file_32_rrw.vhd

DLX CPU VHDL CODE UNIVERSITY

--
-- $RCSfile: reg_file_32_rrw.vhd,v $
-- $Revision: 1.1 $
-- $Author: petera $
-- $Date: 90/06/21 10:02:59 $
--

use work.dp32_types.all;

entity reg_file_32_rrwr is
  generic (depth : positive;		  -- number of address bits
      	    Tpd : Time := unit_delay;
      	    Tac : Time := unit_delay);
  port (a1 : in bit_vector(depth-1 downto 0);
  	q1 : out bus_bit_32 bus;
	en1 : in bit;
	a2 : in bit_vector(depth-1 downto 0);
	q2 : out bus_bit_32 bus;
	en2 : in bit;
	a3 : in bit_vector(depth-1 downto 0);
	d3 : in bit_32;
	en3 : in bit;
	a4 : in bit_vector(depth-1 downto 0);
	q4 : out bus_bit_32 bus;
	en4 : in bit);
end reg_file_32_rrwr;

architecture behaviour of reg_file_32_rrwr is
  
begin

  reg_file: process (a1, en1, a2, en2, a3, d3, en3,a4,en4)

    subtype reg_addr is natural range 0 to power(2,(depth-1));
    type register_array is array (reg_addr) of bit_32;
    
    variable registers : register_array;

  begin
    if en3 = '1' then
      registers(bits_to_natural(a3)) := d3;
    end if;
    if en1 = '1' then
      q1 <= registers(bits_to_natural(a1)) after Tac;
    else
      q1 <= null after Tpd;
    end if;
    if en2 = '1' then
      q2 <= registers(bits_to_natural(a2)) after Tac;
    else
      q2 <= null after Tpd;
    end if;
    if en4 = '1' then
      q4 <= registers(bits_to_natural(a4)) after Tac;
    else
      q4 <= null after Tpd;
    end if;
    registers(0):=X"0000_0000";	 
  end process reg_file;

end behaviour;