subtractor_unsigned.vhd

DLX CPU VHDL CODE UNIVERSITY

use work.dp32_types.all;

entity subtractor_unsigned is
    generic (width : positive);
    port(a,b : in bit_vector(width-1 downto 0);
         y : out bit_vector(width-1 downto 0);
	 n,z : out bit);
end subtractor_unsigned;


architecture behaviour of subtractor_unsigned is
begin


main : process (a,b)

variable t: bit_vector(width-1 downto 0);
begin
--wait for 1 ns;

int_to_bits(bits_to_uint(a)-bits_to_uint(b) ,t);
y<=t;

if(bits_to_uint(a)-bits_to_uint(b) = 0) then
  z<='1';
else
  if(bits_to_uint(a)-bits_to_uint(b) < 0) then
    n<='1';
  else
    n<='0';
  end if;	


  z<='0';
end if;


end process;

end behaviour;