makefile

DLX CPU VHDL CODE UNIVERSITY

#
# $RCSfile: makefile,v $
# $Revision: 1.1 $
# $Author: petera $
# $Date: 90/06/22 12:54:33 $
#
#
# Build description file for dp32 processor simulation
#

PROG = vcom


.SUFFIXES :

# ----------------------------------------------------------------
# Package dp32_types: common to all dp32 models
# ----------------------------------------------------------------

dp32_types : DP32_TYPES.sim DP32_TYPES__.sim 

DP32_TYPES.sim  DP32_TYPES__.sim \
 : dp32_types.vhd
	$(PROG) dp32_types.vhd

# ----------------------------------------------------------------
# Entity dp32: interface of the DP32 processor model
# ----------------------------------------------------------------

dp32_entity : DP32.sim

DP32.sim \
 : DP32_TYPES.sim \
   dp32_entity.vhd
	$(PROG) dp32_entity.vhd

# ----------------------------------------------------------------
# Architecture behaviour of dp32
# ----------------------------------------------------------------

dp32_behaviour : DP32__BEHAVIOUR.sim

DP32__BEHAVIOUR.sim \
 : DP32_TYPES.sim DP32.sim \
   dp32_behaviour.vhd
	$(PROG) dp32_behaviour.vhd

# ----------------------------------------------------------------
# Architecture structure of dp32: register transfer level
# ----------------------------------------------------------------

dp32_rtl : DP32__RTL.sim
DP32__RTL.sim  : DP32_TYPES.sim DP32.sim ALU_32_TYPES.sim dp32_rtl.vhd
	$(PROG) dp32_rtl.vhd


# ----------------------------------------------------------------
# Entity and architecture behaviour of reg_file_32_rrw
# ----------------------------------------------------------------

reg_file_32_rrw : REG_FILE_32_RRW.sim REG_FILE_32_RRW__BEHAVIOUR.sim
REG_FILE_32_RRW.sim  REG_FILE_32_RRW__BEHAVIOUR.sim  : DP32_TYPES.sim    reg_file_32_rrw.vhd
	$(PROG) reg_file_32_rrw.vhd

reg_file_32_rrww : REG_FILE_32_RRWW.sim REG_FILE_32_RRWW__BEHAVIOUR.sim
REG_FILE_32_RRWW.sim  REG_FILE_32_RRWW__BEHAVIOUR.sim  : DP32_TYPES.sim    reg_file_32_rrww.vhd
	$(PROG) reg_file_32_rrww.vhd

# ----------------------------------------------------------------
# Entity and architecture behaviour of mux2
# ----------------------------------------------------------------

mux2 : MUX2.sim MUX2__BEHAVIOUR.sim
MUX2.sim  MUX2__BEHAVIOUR.sim  : DP32_TYPES.sim    mux2.vhd 
	$(PROG) mux2.vhd

mux4 : MUX4.sim MUX4__BEHAVIOUR.sim
MUX4.sim  MUX4__BEHAVIOUR.sim  : DP32_TYPES.sim    mux4.vhd 
	$(PROG) mux4.vhd


mux8 : MUX8.sim MUX2__BEHAVIOUR.sim
MUX8.sim  MUX8__BEHAVIOUR.sim  : DP32_TYPES.sim    mux8.vhd 
	$(PROG) mux8.vhd

# ----------------------------------------------------------------
# Package ALU_32_types: types for ALU_32
# ----------------------------------------------------------------

ALU_32_types : ALU_32_TYPES.sim

ALU_32_TYPES.sim \
 : ALU_32_types.vhd
	$(PROG) ALU_32_types.vhd

# ----------------------------------------------------------------
# Entity and architecture behaviour of ALU_32
# ----------------------------------------------------------------

ALU_32 : ALU_32.sim ALU_32__BEHAVIOUR.sim 

ALU_32.sim  ALU_32__BEHAVIOUR.sim \
 : DP32_TYPES.sim ALU_32_TYPES.sim \
   ALU_32.vhd 
	$(PROG) ALU_32.vhd

# ----------------------------------------------------------------
# Entity and architecture behaviour of cond_code_comparator
# ----------------------------------------------------------------

cond_code_comparator : COND_CODE_COMPARATOR.sim COND_CODE_COMPARATOR__BEHAVIOUR.sim

COND_CODE_COMPARATOR.sim  COND_CODE_COMPARATOR__BEHAVIOUR.sim \
 : DP32_TYPES.sim \
   cond_code_comparator 
	$(PROG) cond_code_comparator.vhd

# ----------------------------------------------------------------
# Entity and architecture behaviour of PC_reg
# ----------------------------------------------------------------

PC_reg : PC_REG.sim PC_REG__BEHAVIOUR.sim 

PC_REG.sim  PC_REG__BEHAVIOUR.sim \
 : DP32_TYPES.sim \
   PC_reg.vhd 
	$(PROG) PC_reg.vhd

# ----------------------------------------------------------------
# Entity and architecture behaviour of buffer_32
# ----------------------------------------------------------------

buffer_32 : BUFFER_32.sim BUFFER_32__BEHAVIOUR.sim 

BUFFER_32.sim  BUFFER_32__BEHAVIOUR.sim \
 : DP32_TYPES.sim \
   buffer_32.vhd 
	$(PROG) buffer_32.vhd

# ----------------------------------------------------------------
# Entity and architecture behaviour of signext_8_32
# ----------------------------------------------------------------

signext_8_32 : SIGNEXT_8_32.sim SIGNEXT_8_32__BEHAVIOUR.sim
SIGNEXT_8_32.sim  SIGNEXT_8_32__BEHAVIOUR.sim  : DP32_TYPES.sim    signext_8_32.vhd 
	$(PROG) signext_8_32.vhd

signext_16_32 : SIGNEXT_16_32.sim SIGNEXT_16_32__BEHAVIOUR.sim
SIGNEXT_16_32.sim  SIGNEXT_16_32__BEHAVIOUR.sim  : DP32_TYPES.sim    signext_16_32.vhd 
	$(PROG) signext_16_32.vhd

signext_26_32 : SIGNEXT_26_32.sim SIGNEXT_26_32__BEHAVIOUR.sim
SIGNEXT_26_32.sim  SIGNEXT_26_32__BEHAVIOUR.sim  : DP32_TYPES.sim    signext_26_32.vhd 
	$(PROG) signext_26_32.vhd

# ----------------------------------------------------------------
# Entity and architecture behaviour of latch
# ----------------------------------------------------------------

latch : LATCH.sim LATCH__BEHAVIOUR.sim

LATCH.sim LATCH__BEHAVIOUR.sim \
 : DP32_TYPES.sim \
   latch.vhd 
	$(PROG) latch.vhd

# ----------------------------------------------------------------
# Entity and architecture behaviour of latch_buffer_32
# ----------------------------------------------------------------

latch_buffer_32 : LATCH_BUFFER_32.sim LATCH_BUFFER_32__BEHAVIOUR.sim

LATCH_BUFFER_32.sim  LATCH_BUFFER_32__BEHAVIOUR.sim \
 : DP32_TYPES.sim \
   latch_buffer_32.vhd 
	$(PROG) latch_buffer_32.vhd

# ----------------------------------------------------------------
# Entity and architecture behaviour of memory
# ----------------------------------------------------------------
memory : MEMORY.sim MEMORY__BEHAVIOUR.sim
MEMORY.sim  MEMORY__BEHAVIOUR.sim : DP32_TYPES.sim  memory.vhd
	$(PROG) memory.vhd

convert : CONVERT.sim CONVERT__BEHAVIOUR.sim
CONVERT.sim CONVERT__BEHAVIOUR.sim : DP32_TYPES.sim  convert.vhd
	$(PROG) convert.vhd

fp_adder : FP_ADDER.sim FP_ADDER__BEHAVIOUR.sim
FP_ADDER.sim  FP_ADDER__BEHAVIOUR.sim : DP32_TYPES.sim  fp_adder.vhd
	$(PROG) fp_adder.vhd

FP_MULT : FP_MULT.sim FP_MULT__BEHAVIOUR.sim
FP_MULT.sim  FP_MULT__BEHAVIOUR.sim : DP32_TYPES.sim  FP_mult.vhd
	$(PROG) FP_mult.vhd

DIVIDER.sim DIVIDER__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) divider.vhd

XOR.sim XOR__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) xor.vhd

MANT_EXT.sim MANT_EXT__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) mant_ext.vhd

LEFTSHIFT.sim LEFTSHIFT__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) leftshift.vhd

LINKS.sim LINKS__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) Links.vhd

LINK2.sim LINK2__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) Link2.vhd

SUBTRACTOR_SIGNED.sim SUBTRACTOR_SIGNED__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) subtractor_signed.vhd

ADDER_SIGNED.sim ADDER_SIGNED__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) adder_signed.vhd

SUBTRACTOR_UNSIGNED.sim SUBTRACTOR_UNSIGNED__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) subtractor_unsigned.vhd

ADDER_UNSIGNED.sim ADDER_UNSIGNED__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) adder_unsigned.vhd

OR.sim OR__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) or.vhd

FP_UTILS.sim FP_UTILS__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) fp_utils.vhd

FP_ROUNDER.sim FP_ROUNDER__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) fp_rounder.vhd

FLAGS_REPLACE.sim FLAGS_REPLACE__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) flags_replace.vhd

GEQ.sim GEQ__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) geq.vhd

CREATE_FLAGS.sim CREATE_FLAGS__BEHAVIOUR.sim : DP32_TYPES.sim
	$(PROG) create_flags.vhd

FP_DIV : FP_DIV.sim FP_DIV__BEHAVIOUR.sim
FP_DIV.sim  FP_DIV__BEHAVIOUR.sim : DP32_TYPES.sim  fp_div.vhd
	$(PROG) fp_div.vhd

multdiv : MULTDIV.sim MULTDIV__BEHAVIOUR.sim
MULTDIV.sim  MULTDIV__BEHAVIOUR.sim : DP32_TYPES.sim  multdiv.vhd
	$(PROG) multdiv.vhd

microrom : MICROROM.sim MICROROM__BEHAVIOUR.sim
MICROROM.sim  MICROROM__BEHAVIOUR.sim : DP32_TYPES.sim  microrom.vhd
	$(PROG) microrom.vhd

shifter : SHIFTER.sim SHIFTER__BEHAVIOUR.sim
SHIFTER.sim SHIFTER__BEHAVIOUR.sim : DP32_TYPES.sim  shifter.vhd
	$(PROG) shifter.vhd

IF_Unit : IF_UNIT.sim IF_UNIT__BEHAVIOUR.sim
IF_UNIT.sim  IF_UNIT__BEHAVIOUR.sim : DP32_TYPES.sim  IF_Unit.vhd
	$(PROG) IF_Unit.vhd

# ----------------------------------------------------------------
# Entity and architecture structure of dp32_test:
#   Test bench for dp32 processor
# ----------------------------------------------------------------

dp32_test \
 : CLOCK_GEN.sim CLOCK_GEN__BEHAVIOUR.sim \
   DP32_TEST.sim DP32_TEST__STRUCTURE.sim 

CLOCK_GEN.sim  CLOCK_GEN__BEHAVIOUR.sim + \
DP32_TEST.sim  DP32_TEST__STRUCTURE.sim \
 : DP32_TYPES.sim \
   dp32_test.vhd
	$(PROG) dp32_test.vhd

# ----------------------------------------------------------------
# Configuration dp32_behaviour_test of dp32_test
# ----------------------------------------------------------------

dp32_behaviour_test : DP32_BEHAVIOUR_TEST.sim

DP32_BEHAVIOUR_TEST.sim \
 : DP32_TYPES.sim DP32_TYPES__.sim \
   CLOCK_GEN.sim CLOCK_GEN__BEHAVIOUR.sim \
   DP32_TEST.sim DP32_TEST__STRUCTURE.sim \
   MEMORY.sim MEMORY__BEHAVIOUR.sim \
   DP32.sim DP32__BEHAVIOUR.sim \
   dp32_behaviour_test.vhd
	$(PROG) dp32_behaviour_test.vhd

# ----------------------------------------------------------------
# Configuration dp32_rtl_test of dp32_test
# ----------------------------------------------------------------

dp32_rtl_test : DP32_RTL_TEST.sim

test \
 : DP32_TYPES.sim DP32_TYPES__.sim \
   DIVIDER.sim DIVIDER__BEHAVIOUR.sim \
   SUBTRACTOR_SIGNED.sim SUBTRACTOR_SIGNED__BEHAVIOUR.sim \
   ADDER_SIGNED.sim ADDER_SIGNED__BEHAVIOUR.sim \
   SUBTRACTOR_UNSIGNED.sim SUBTRACTOR_UNSIGNED__BEHAVIOUR.sim \
   ADDER_UNSIGNED.sim ADDER_UNSIGNED__BEHAVIOUR.sim \
   FLAGS_REPLACE.sim FLAGS_REPLACE.sim \
   XOR.sim XOR__BEHAVIOUR.sim \
   FP_ROUNDER.sim FP_ROUNDER__BEHAVIOUR.sim \
   CREATE_FLAGS.sim CREATE_FLAGS__BEHAVIOUR.sim \
   LEFTSHIFT.sim LEFTSHIFT__BEHAVIOUR.sim \
   OR.sim OR__BEHAVIOUR.sim \
   FP_UTILS.sim FP_UTILS__BEHAVIOUR.sim \
   GEQ.sim GEQ__BEHAVIOUR.sim \
   LINKS.sim LINKS__BEHAVIOUR.sim \
   LINK2.sim LINK2__BEHAVIOUR.sim \
   MANT_EXT.sim MANT_EXT__BEHAVIOUR.sim \
   CLOCK_GEN.sim CLOCK_GEN__BEHAVIOUR.sim \
   DP32_TEST.sim DP32_TEST__STRUCTURE.sim \
   IF_UNIT.sim IF_UNIT__BEHAVIOUR.sim \
   MEMORY.sim MEMORY__BEHAVIOUR.sim \
   CONVERT.sim CONVERT__BEHAVIOUR.sim \
   FP_ADDER.sim FP_ADDER__BEHAVIOUR.sim \
   MULTDIV.sim MULTDIV__BEHAVIOUR.sim \
   FP_MULT.sim FP_MULT__BEHAVIOUR.sim \
   FP_DIV.sim FP_DIV__BEHAVIOUR.sim \
   MICROROM.sim MICROROM__BEHAVIOUR.sim \
   SHIFTER.sim SHIFTER__BEHAVIOUR.sim \
   DP32.sim DP32__RTL.sim \
   REG_FILE_32_RRW.sim REG_FILE_32_RRW__BEHAVIOUR.sim \
   REG_FILE_32_RRWW.sim REG_FILE_32_RRWW__BEHAVIOUR.sim \
   MUX2.sim MUX2__BEHAVIOUR.sim \
   MUX4.sim MUX4__BEHAVIOUR.sim \
   MUX8.sim MUX8__BEHAVIOUR.sim \
   ALU_32.sim ALU_32__BEHAVIOUR.sim \
   BUFFER_32.sim BUFFER_32__BEHAVIOUR.sim  \
   SIGNEXT_8_32.sim SIGNEXT_8_32__BEHAVIOUR.sim \
   SIGNEXT_16_32.sim SIGNEXT_16_32__BEHAVIOUR.sim \
   SIGNEXT_26_32.sim SIGNEXT_26_32__BEHAVIOUR.sim \
   LATCH.sim LATCH__BEHAVIOUR.sim \
   LATCH_BUFFER_32.sim LATCH_BUFFER_32__BEHAVIOUR.sim \
   dp32_rtl_test.vhd
	$(PROG) dp32_rtl_test.vhd