dp32_types2.vhd

DLX CPU VHDL CODE UNIVERSITY

library ieee;

use ieee.std_logic_1164.all;


package dp32_types is

  constant unit_delay : Time := 1 ns;
  
  type bool_to_bit_table is array (boolean) of bit;

  constant bool_to_bit : bool_to_bit_table;

  type bit_32_array is array (integer range <>) of bit_32;
  function resolve_bit_32 (driver : in bit_32_array) return bit_32;
  subtype bus_bit_32 is resolve_bit_32 bit_32;
  
  subtype bit_6 is bit_vector(5 downto 0);
  subtype bit_16 is bit_vector (15 downto 0);
  subtype bit_26 is bit_vector (25 downto 0);
  subtype bit_5 is bit_vector (4 downto 0);
  subtype bit_2 is bit_vector (1 downto 0);
  subtype bit_8 is bit_vector (7 downto 0); 
  subtype bit_4 is bit_vector (3 downto 0);

  subtype CC_bits is bit_vector(2 downto 0);
  subtype cm_bits is bit_vector(3 downto 0);

  -- opcodes
  constant op_special : bit_6 := "000000";
  constant op_lw      : bit_6 := "100011";
  constant op_sw      : bit_6 := "101011";
  constant op_lf      : bit_6 := "100110";
  constant op_sf      : bit_6 := "101110";
  constant op_fparith : bit_6 := "000001";
  constant op_j       : bit_6 := "000010";
  constant op_jal     : bit_6 := "000011";
  constant op_jr      : bit_6 := "010010";
  constant op_jalr    : bit_6 := "010011";
  constant op_addi    : bit_6 := "001000";
  constant op_subi    : bit_6 := "001010";
  constant op_andi    : bit_6 := "001100";
  constant op_ori     : bit_6 := "001101";
  constant op_xori    : bit_6 := "001110";
  constant op_lhi     : bit_6 := "001111";
  constant op_addui   : bit_6 := "001001";
  constant op_subui   : bit_6 := "001011";
  constant op_beqz    : bit_6 := "000100";
  constant op_bnez    : bit_6 := "000101";
  constant op_lb      : bit_6 := "100000";
  constant op_lbu     : bit_6 := "100100";
  constant op_seqi    : bit_6 := "011000";
  constant op_snei    : bit_6 := "011001";
  constant op_sgei    : bit_6 := "011101";
  constant op_slei    : bit_6 := "011100";
  constant op_sgti    : bit_6 := "011011";
  constant op_slti    : bit_6 := "011010";
  constant op_slli    : bit_6 := "010100";
  constant op_srli    : bit_6 := "010110";
  constant op_srai    : bit_6 := "010111";


  -- special opcodes  
  constant op_nop   : bit_6 := "000000";
  constant op_add   : bit_6 := "100000";
  constant op_addu  : bit_6 := "100001";
  constant op_sub   : bit_6 := "100010";
  constant op_subu  : bit_6 := "100011";
  constant op_and   : bit_6 := "100100";
  constant op_or    : bit_6 := "100101";
  constant op_xor   : bit_6 := "100110";
  constant op_sll   : bit_6 := "000100";
  constant op_trap  : bit_6 := "001100";
  constant op_srl   : bit_6 := "000110";
  constant op_sra   : bit_6 := "000111";
  constant op_seq   : bit_6 := "101000";
  constant op_sne   : bit_6 := "101001";
  constant op_slt   : bit_6 := "101010";
  constant op_sge   : bit_6 := "101101";
  constant op_sgt   : bit_6 := "101011"; 
  constant op_sle   : bit_6 := "101100";
  -- fp opcodes 
  constant op_mult  : bit_6 := "001110";
  constant op_div   : bit_6 := "001111";
  constant op_multu : bit_6 := "010110";
  constant op_divu  : bit_6 := "010111";


  -- assume twos compliment integers:

  function bits_to_int (bits : in bit_vector) return integer;

  function vector_to_string (bits : in bit_vector) return string;

  function bits_to_uint (bits : in bit_vector) return integer;
  
  function bits_to_natural (bits : in bit_vector) return natural;
 
  function add ( bits : in bit_vector; num : in natural) return bit_vector; 

  function bit_to_std_logic (b: in bit) return std_logic;
  
  procedure int_to_bits (int : in integer; bits : out bit_vector);
  
  procedure natural_to_bits (n : in natural; bits : out bit_vector); 

  function power (x , p : in natural) return natural;

end dp32_types;

package body dp32_types is

  constant bool_to_bit : bool_to_bit_table :=
    (false => '0', true => '1');

  function resolve_bit_32 (driver : in bit_32_array) return bit_32 is
    constant float_value : bit_32 := X"0000_0000";
    variable result : bit_32 := float_value;
  begin
    for i in driver'range loop
      result := result or driver(i);
    end loop;
    return result;
  end resolve_bit_32;

  function power (x , p : in natural) return natural is
  variable r: natural :=x;
  variable i: natural :=0;
  begin
    for i in p downto 1 loop
      r:=r*x;
    end loop;

  return r;
  end power;


  function bits_to_int (bits : in bit_vector) return integer is
    variable temp : bit_vector(bits'range);
    variable result : integer := 0;
  begin
    if bits(bits'left) = '1' then	  -- negative number
      temp := not bits;
    else
      temp := bits;
    end if;
    for index in bits'range loop	  -- sign bit of temp = '0'
      result := result * 2 + bit'pos(temp(index));
    end loop;
    if bits(bits'left) = '1' then
      result := (-result) - 1;
    end if;
    return result;
  end bits_to_int;

  function bits_to_uint (bits : in bit_vector) return integer is
    variable temp : bit_vector(bits'range);
    variable result : integer := 0;
  begin
   
      temp := bits;
   
    for index in bits'range loop	  -- sign bit of temp = '0'
      result := result * 2 + bit'pos(temp(index));
    end loop;

    return result;
  end bits_to_uint;

  function bits_to_natural (bits : in bit_vector) return natural is
    variable result : natural := 0;
  begin
    for index in bits'range loop
      result := result * 2 + bit'pos(bits(index));
    end loop;
    return result;
  end bits_to_natural;

  function add ( bits : in bit_vector; num : in natural) return bit_vector is 
    variable temp : natural;
    variable r : bit_vector(bits'range);
  begin
    temp:=bits_to_natural(bits);
    temp:=temp+num;
    natural_to_bits(temp,r);    
    return r;
  end add;
  


  function vector_to_string (bits : in bit_vector) return string is
	variable temp : string( bits'left+1 downto 1 );
  begin
	for i in bits'reverse_range loop
		if(bits(i)='0') then
			temp(i+1):='0';
	        else
			temp(i+1):='1';
		end if;

	end loop;
  return temp;
  end vector_to_string;



  procedure int_to_bits (int : in integer; bits : out bit_vector) is
    variable temp : integer;
    variable result : bit_vector(bits'range);
  begin
    if int < 0 then
      temp := -(int+1);
    else
      temp := int;
    end if;
    for index in bits'reverse_range loop
      result(index) := bit'val(temp rem 2);
      temp := temp / 2;
    end loop;
    if int < 0 then
      result := not result;
      result(bits'left) := '1';
    end if;
    bits := result;
  end int_to_bits;

  procedure natural_to_bits (n : in natural; bits : out bit_vector) is
    variable temp : natural;
    variable result : bit_vector(bits'range);
  begin
    if n < 0 then
      temp := -(n+1);
    else
      temp := n;
    end if;
    for index in bits'reverse_range loop
      result(index) := bit'val(temp rem 2);
      temp := temp /2;
    end loop;
    if n < 0 then
      result := not result;
      result(bits'left) := '1';
    end if;
    bits := result;
  end natural_to_bits;


  function bit_to_std_logic (b: in bit) return std_logic is
  --variable r: std_logic:=0;
  begin
  if (b='1') then
	return '1';
  end if;
  return '0';

  
  end bit_to_std_logic;

end dp32_types;