signext_26_32.vhd

来自「DLX CPU VHDL CODE UNIVERSITY」· VHDL 代码 · 共 29 行

use work.dp32_types.all;

entity signext_26_32 is
  generic (Tpd : Time := unit_delay);
  port (a : in bit_26;
      	b : out bus_bit_32 bus;
	en : in bit);
end signext_26_32;

architecture behaviour of signext_26_32 is

begin

  b_driver: process (en, a)
  begin
    if en = '1' then
      b(25 downto 0) <= a after Tpd;
      if a(25) = '1' then
      	b(31 downto 26) <= "111111" after Tpd;
      else
      	b(31 downto 26) <= "000000" after Tpd;
      end if;
    else
      b <= null after Tpd;
    end if;
  end process b_driver;

end behaviour;