user_cfg.scr

ccx的verilog代码,opensparc 的源代码

# ========== Copyright Header Begin ==========================================
# 
# OpenSPARC T1 Processor File: user_cfg.scr
# Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
# 
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
# 
# The above named program is distributed in the hope that it will be 
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
# 
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
# 
# ========== Copyright Header End ============================================

source -echo -verbose $dv_root/design/sys/synopsys/script/project_io_cfg.scr

set rtl_files {\
lib/u1/u1.behV \
lib/m1/m1.behV \
design/sys/iop/common/rtl/swrvr_clib.v \
design/sys/iop/common/rtl/swrvr_dlib.v \
design/sys/iop/ccx/rtl/cpx_buf_top.v  \
design/sys/iop/ccx/rtl/cpx_buf_pt.v  \
design/sys/iop/ccx/rtl/cpx_datacx2_ff.v  \
design/sys/iop/ccx/rtl/cpx_io_grant_ff.v  \
design/sys/iop/ccx/rtl/io_cpx_reqdata_ff.v  \

design/sys/iop/ccx/rtl/cpx_buf_pm.v \
design/sys/iop/ccx/rtl/cpx_buf_pm_even.v \
design/sys/iop/ccx/rtl/cpx_buf_p0.v \
design/sys/iop/ccx/rtl/cpx_buf_p0_even.v \
design/sys/iop/ccx/rtl/cpx_buf_p1.v \
design/sys/iop/ccx/rtl/cpx_fpbuf_p0.v \
design/sys/iop/ccx/rtl/cpx_fpbuf_p1.v \
design/sys/iop/ccx/rtl/cpx_buf_pdl_even.v \
design/sys/iop/ccx/rtl/cpx_buf_p3.v \
design/sys/iop/ccx/rtl/cpx_buf_pdr_even.v \
design/sys/iop/ccx/rtl/cpx_buf_p4.v \
design/sys/iop/ccx/rtl/cpx_buf_p4_even.v \
design/sys/iop/ccx/rtl/cpx_databuf_ca.v \
design/sys/iop/ccx/rtl/cpx_databuf_ca2.v \
design/sys/iop/ccx/rtl/cpx_buf_io.v \

}

set mix_files {}
set top_module cpx_buf_top

set include_paths {\
design/sys/iop/include \
}

set black_box_libs {}
set black_box_designs {}
set mem_libs {}
set dont_touch_modules {}
set compile_effort   "medium"

set compile_flatten_all 1

set compile_no_new_cells_at_top_level false

set default_clk rclk
set default_clk_freq  1200
set default_setup_skew  0.1
set default_hold_skew  0.1
set default_clk_transition  0.04
set clk_list {                        \
                {rclk   1200.0   0.100   0.100   0.040}        \
}

set ideal_net_list {}
set false_path_list {}
set enforce_input_fanout_one     0
set allow_outport_drive_innodes  1
set skip_scan            0
set add_lockup_latch     false
set chain_count          1
set scanin_port_list     {}
set scanout_port_list    {}
set scanenable_port      global_shift_enable
set has_test_stub        1
set scanenable_pin       test_stub_no_bist/se
set long_chain_so_0_net  long_chain_so_0
set short_chain_so_0_net short_chain_so_0
set so_0_net             so_0
set insert_extra_lockup_latch 0
set extra_lockup_latch_clk_list {}