sdram_top_tb_runtest.do

sdram controller vhdl

SetActiveLib -work
comp -include "$DSN\src\mt48lc2m32b2_2.vhd" 
comp -include "$DSN\src\SDR_CTRL.vhd" 
comp -include "$DSN\src\SDRAM_32.vhd" 
comp -include "$DSN\src\sdram_top.vhd" 
comp -include "$DSN\src\TestBench\sdram_top_TB.vhd" 
asim TESTBENCH_FOR_sdram_top 
wave 
wave -noreg CLK
wave -noreg WnR
wave -noreg nAS
wave -noreg nRST
wave -noreg ADDR
wave -noreg DIN
wave -noreg nLBE
wave -noreg DTACK
wave -noreg DOUT
run 600.00 us
# The following lines can be used for timing simulation
# acom <backannotated_vhdl_file_name>
# comp -include "$DSN\src\TestBench\sdram_top_TB_tim_cfg.vhd" 
# asim TIMING_FOR_sdram_top