cnt24.vhd

来自「EDA设计实验」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt24 is
    port(hh,hl:buffer std_logic_vector(3 downto 0);
         clk:in std_logic
         );
end cnt24;
architecture behave of cnt24 is
begin
    process(clk)
    begin
        if clk'event and clk='1' then
            if hl=9 then
                hl<="0000";
                hh<=hh+1;
            elsif hl=3 then
                if hh=2 then
                    hh<="0000";
                    hl<="0000";
                else
                    hl<=hl+1;
                end if;
            else 
                hl<=hl+1;
            end if;
         end if;
    end process;
end behave;