adc_test.tan.rpt

来自「这是sd/mmc卡程序的第三部分」· RPT 代码 · 共 189 行 · 第 1/5 页

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                      ; To                                                                                                                                                                          ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 4.680 ns                         ; sdo                                                                                                       ; adc_base:inst|recv_data_r[1]                                                                                                                                                ; --                           ; sclk                         ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 11.588 ns                        ; adc_base:inst|sdi_r                                                                                       ; sdi                                                                                                                                                                         ; sclk                         ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 3.026 ns                         ; altera_internal_jtag~TDO                                                                                  ; altera_reserved_tdo                                                                                                                                                         ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 2.089 ns                         ; altera_internal_jtag~TMSUTAP                                                                              ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]                                                                                                     ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'sclk'                         ; N/A   ; None          ; 140.53 MHz ( period = 7.116 ns ) ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_address_reg11 ; sclk                         ; sclk                         ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 142.45 MHz ( period = 7.020 ns ) ; sld_hub:sld_hub_inst|jtag_debug_mode_usr1                                                                 ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                                                ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                           ;                                                                                                                                                                             ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;