__projnav.log

this is a vhdl code for usb

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JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    IOSwitch.vhd
Scanning    PDIUSBD12_Package.vhd
Scanning    USB_Package.vhd
Scanning    IOSwitch.vhd
Writing IOSwitch.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    RequestHandler.vhd
Scanning    PDIUSBD12_Package.vhd
Scanning    USB_Package.vhd
Scanning    RequestHandler.vhd
Writing RequestHandler.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    USBSoftLock.vhd
Scanning    PDIUSBD12_Package.vhd
Scanning    USB_Package.vhd
Scanning    USBSoftLock.vhd
Writing USBSoftLock.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    usbsoftlock_TB.vhd
Scanning    PDIUSBD12_Package.vhd
Scanning    USB_Package.vhd
Scanning    usbsoftlock_TB.vhd
Writing usbsoftlock_TB.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/Firmware/USB_Package.vhd in Library work.
Compiling vhdl file D:/Firmware/PDIUSBD12_Package.vhd in Library work.
Compiling vhdl file D:/Firmware/FrequencyDivider.vhd in Library work.
Entity <frequencydivider> (Architecture <frequencydivider>) compiled.
Compiling vhdl file D:/Firmware/EdgeController.vhd in Library work.
Entity <edgecontroller> (Architecture <edgecontroller>) compiled.
Compiling vhdl file D:/Firmware/DeviceTranseiver.vhd in Library work.
Entity <devicetranseiver> (Architecture <devicetranseiver>) compiled.
Compiling vhdl file D:/Firmware/IOSwitch.vhd in Library work.
Entity <ioswitch> (Architecture <ioswitch>) compiled.
Compiling vhdl file D:/Firmware/RequestHandler.vhd in Library work.
Entity <requesthandler> (Architecture <requesthandler>) compiled.
Compiling vhdl file D:/Firmware/USBSoftLock.vhd in Library work.
Entity <usbsoftlock> (Architecture <usbsoftlock>) compiled.

Completed process "Check Syntax".



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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/Firmware/USB_Package.vhd in Library work.
Architecture usb_package of Entity usb_package is up to date.
Compiling vhdl file D:/Firmware/PDIUSBD12_Package.vhd in Library work.
Architecture pdiusbd12_package of Entity pdiusbd12_package is up to date.
Compiling vhdl file D:/Firmware/FrequencyDivider.vhd in Library work.
Architecture frequencydivider of Entity frequencydivider is up to date.
Compiling vhdl file D:/Firmware/EdgeController.vhd in Library work.
Architecture edgecontroller of Entity edgecontroller is up to date.
Compiling vhdl file D:/Firmware/DeviceTranseiver.vhd in Library work.
Architecture devicetranseiver of Entity devicetranseiver is up to date.
Compiling vhdl file D:/Firmware/IOSwitch.vhd in Library work.
Architecture ioswitch of Entity ioswitch is up to date.
Compiling vhdl file D:/Firmware/RequestHandler.vhd in Library work.
Architecture requesthandler of Entity requesthandler is up to date.
Compiling vhdl file D:/Firmware/USBSoftLock.vhd in Library work.
Architecture usbsoftlock of Entity usbsoftlock is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <usbsoftlock> (Architecture <usbsoftlock>).
Entity <usbsoftlock> analyzed. Unit <usbsoftlock> generated.

Analyzing generic Entity <frequencydivider> (Architecture <frequencydivider>).
	div_factor = 15
Entity <frequencydivider> analyzed. Unit <frequencydivider> generated.

Analyzing Entity <edgecontroller> (Architecture <edgecontroller>).
Entity <edgecontroller> analyzed. Unit <edgecontroller> generated.

Analyzing Entity <devicetranseiver> (Architecture <devicetranseiver>).
INFO:Xst:1304 - Contents of register <config> in unit <devicetranseiver> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <step<7>> in unit <devicetranseiver> never changes during circuit operation. The register is replaced by logic.
Entity <devicetranseiver> analyzed. Unit <devicetranseiver> generated.

Analyzing Entity <ioswitch> (Architecture <ioswitch>).
Entity <ioswitch> analyzed. Unit <ioswitch> generated.

Analyzing Entity <requesthandler> (Architecture <requesthandler>).
INFO:Xst:1304 - Contents of register <rh_state> in unit <requesthandler> never changes during circuit operation. The register is replaced by logic.
Entity <requesthandler> analyzed. Unit <requesthandler> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <requesthandler>.
    Related source file is D:/Firmware/RequestHandler.vhd.
WARNING:Xst:646 - Signal <rh_state<0>> is assigned but never used.
    Found 8-bit register for signal <cmd>.
    Found 1-bit register for signal <exec_n>.
    Found 1-bit register for signal <address_set>.
    Summary:
	inferred  10 D-type flip-flop(s).
Unit <requesthandler> synthesized.


Synthesizing Unit <ioswitch>.
    Related source file is D:/Firmware/IOSwitch.vhd.
    Found 8-bit tristate buffer for signal <data_tmp>.
    Summary:
	inferred   8 Tristate(s).
Unit <ioswitch> synthesized.


Synthesizing Unit <devicetranseiver>.
    Related source file is D:/Firmware/DeviceTranseiver.vhd.
WARNING:Xst:646 - Signal <config> is assigned but never used.
    Using one-hot encoding for signal <ts_state>.
    Using one-hot encoding for signal <ih_state>.
    Found 16x25-bit ROM for signal <$n0368>.
    Found 8-bit register for signal <data_out>.
    Found 1-bit register for signal <recv_n>.
    Found 8-bit register for signal <req_type>.
    Found 1-bit register for signal <rd_n>.
    Found 1-bit register for signal <wr_n>.
    Found 7-bit register for signal <step<6:0>>.
    Found 1-bit register for signal <a0>.
    Found 8-bit adder for signal <$n0353> created at line 178.
    Found 8-bit adder for signal <$n0354> created at line 363.
    Found 8-bit adder for signal <$n0355> created at line 142.
    Found 8-bit adder for signal <$n0357> created at line 142.
    Found 8-bit comparator greatequal for signal <$n0358> created at line 484.
    Found 8-bit comparator greater for signal <$n0359> created at line 518.
    Found 8-bit comparator greater for signal <$n0360> created at line 521.
    Found 8-bit comparator greater for signal <$n0361> created at line 532.
    Found 8-bit comparator greater for signal <$n0362> created at line 538.
    Found 8-bit adder for signal <$n0366> created at line 444.
    Found 8-bit subtractor for signal <$n0376> created at line 481.
    Found 8-bit comparator equal for signal <$n0385> created at line 284.
    Found 8-bit comparator equal for signal <$n0393> created at line 364.
    Found 8-bit comparator equal for signal <$n0397> created at line 432.
    Found 8-bit comparator greatequal for signal <$n0398> created at line 484.
    Found 8-bit comparator greater for signal <$n0405> created at line 300.
    Found 8-bit adder for signal <$n0407> created at line 314.
    Found 8-bit comparator greatequal for signal <$n0408> created at line 315.
    Found 2-bit adder for signal <$n0411> created at line 274.
    Found 8-bit register for signal <active_ep>.
    Found 8-bit register for signal <data_count>.
    Found 8-bit register for signal <data_length>.
    Found 8-bit register for signal <handle_step>.
    Found 6-bit register for signal <ih_state>.
    Found 8-bit register for signal <ir_0>.
    Found 1-bit register for signal <is_receive>.
    Found 1-bit register for signal <is_transmit>.
    Found 25-bit register for signal <last_ts_state>.
    Found 8-bit register for signal <ram_address>.
    Found 8-bit register for signal <read_count>.
    Found 8-bit register for signal <read_in>.
    Found 1-bit register for signal <remote_wakeup>.
    Found 5-bit register for signal <to_read>.
    Found 8-bit register for signal <to_write>.
    Found 2048-bit register for signal <ts_data>.
    Found 25-bit register for signal <ts_state>.
    Found 8-bit register for signal <write_count>.
    Found 26 1-bit 2-to-1 multiplexers.
WARNING:Xst:649 - Inout <suspend> is never used.
    Summary:
	inferred   1 ROM(s).
	inferred 1779 D-type flip-flop(s).
	inferred   8 Adder/Subtracter(s).
	inferred  11 Comparator(s).
Unit <devicetranseiver> synthesized.


Synthesizing Unit <edgecontroller>.
    Related source file is D:/Firmware/EdgeController.vhd.
Unit <edgecontroller> synthesized.