📄 xiaodou2.rpt
字号:
14 - - B -- OUTPUT 0 1 0 0 rxout
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\vhdl\shiyan\juzhenjianpan\xiaodou2.rpt
xiaodou2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 15 DFFE + ! 1 1 1 0 :4
- 6 - B 15 DFFE + ! 1 1 0 2 dout (:6)
- 5 - B 15 DFFE + 0 3 0 2 count2 (:7)
- 4 - B 15 DFFE + 0 2 0 1 count1 (:8)
- 2 - B 15 DFFE + 0 1 0 2 count0 (:9)
- 1 - B 15 OR2 s 1 2 0 3 ~264~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\vhdl\shiyan\juzhenjianpan\xiaodou2.rpt
xiaodou2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl\shiyan\juzhenjianpan\xiaodou2.rpt
xiaodou2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 gclk
Device-Specific Information: d:\vhdl\shiyan\juzhenjianpan\xiaodou2.rpt
xiaodou2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 rst
Device-Specific Information: d:\vhdl\shiyan\juzhenjianpan\xiaodou2.rpt
xiaodou2
** EQUATIONS **
gclk : INPUT;
rst : INPUT;
shuru : INPUT;
-- Node name is ':9' = 'count0'
-- Equation name is 'count0', location is LC2_B15, type is buried.
count0 = DFFE( _EQ001, GLOBAL( gclk), GLOBAL(!rst), VCC, VCC);
_EQ001 = !count0 & _LC1_B15;
-- Node name is ':8' = 'count1'
-- Equation name is 'count1', location is LC4_B15, type is buried.
count1 = DFFE( _EQ002, GLOBAL( gclk), GLOBAL(!rst), VCC, VCC);
_EQ002 = !count0 & count1 & _LC1_B15
# count0 & !count1 & _LC1_B15;
-- Node name is ':7' = 'count2'
-- Equation name is 'count2', location is LC5_B15, type is buried.
count2 = DFFE( _EQ003, GLOBAL( gclk), GLOBAL(!rst), VCC, VCC);
_EQ003 = count0 & count1 & _LC1_B15;
-- Node name is ':6' = 'dout'
-- Equation name is 'dout', location is LC6_B15, type is buried.
!dout = dout~NOT;
dout~NOT = DFFE( _EQ004, GLOBAL( gclk), GLOBAL(!rst), VCC, VCC);
_EQ004 = count2 & !shuru
# !dout & !shuru
# !count2 & !dout;
-- Node name is 'rxout'
-- Equation name is 'rxout', type is output
rxout = _LC3_B15;
-- Node name is ':4'
-- Equation name is '_LC3_B15', type is buried
!_LC3_B15 = _LC3_B15~NOT;
_LC3_B15~NOT = DFFE( _EQ005, GLOBAL( gclk), GLOBAL(!rst), VCC, VCC);
_EQ005 = !dout & !shuru
# !_LC3_B15 & !shuru
# !dout & !_LC3_B15;
-- Node name is '~264~1'
-- Equation name is '~264~1', location is LC1_B15, type is buried.
-- synthesized logic cell
_LC1_B15 = LCELL( _EQ006);
_EQ006 = !count2 & dout & !shuru
# !count2 & !dout & shuru;
Project Information d:\vhdl\shiyan\juzhenjianpan\xiaodou2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,586K
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