📄 dclk.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dclk is
port(clk:in std_logic;
divclk:out std_logic);
end dclk;
architecture dclk_arch of dclk is
begin
process(clk)
variable cnt:std_logic_vector(1 downto 0);
variable a:std_logic;
begin
if clk'event and clk='1' then
if a='0' then
if cnt="11" then
a:='1';
else
cnt:=cnt+1;
end if;
elsif a='1' then
if cnt="00" then
a:='0';
else
cnt:=cnt-1;
end if;
end if;
end if;
divclk<=a;
end process;
end dclk_arch;
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