jizhenjianpanyima.rpt

本源码用VHDL语言实现了用键盘控制米字管显示十进制

  _EQ023 =  kin1 & !kin2 &  kin3 &  _LC8_F7;

-- Node name is '|YIMA:4|:216' 
-- Equation name is '_LC6_F14', type is buried 
_LC6_F14 = LCELL( _EQ024);
  _EQ024 =  _LC1_F7 &  _LC2_F9 &  _LC3_F7 &  _LC4_F14;

-- Node name is '|YIMA:4|:226' 
-- Equation name is '_LC4_F15', type is buried 
_LC4_F15 = LCELL( _EQ025);
  _EQ025 =  kin0 &  _LC1_F7 &  _LC4_F14 &  _LC5_F9;

-- Node name is '|YIMA:4|~236~1' 
-- Equation name is '_LC3_F7', type is buried 
-- synthesized logic cell 
_LC3_F7  = LCELL( _EQ026);
  _EQ026 = !kin0 &  kin1;

-- Node name is '|YIMA:4|:236' 
-- Equation name is '_LC1_F14', type is buried 
_LC1_F14 = LCELL( _EQ027);
  _EQ027 =  _LC2_F9 &  _LC3_F7 &  _LC7_F14;

-- Node name is '|YIMA:4|~246~1' 
-- Equation name is '_LC2_F9', type is buried 
-- synthesized logic cell 
_LC2_F9  = LCELL( _EQ028);
  _EQ028 =  kin2 &  kin3;

-- Node name is '|YIMA:4|~246~2' 
-- Equation name is '_LC5_F9', type is buried 
-- synthesized logic cell 
_LC5_F9  = LCELL( _EQ029);
  _EQ029 = !kin1 &  _LC2_F9;

-- Node name is '|YIMA:4|:282' 
-- Equation name is '_LC5_F15', type is buried 
_LC5_F15 = LCELL( _EQ030);
  _EQ030 =  _LC4_F15 & !_LC6_F14
         #  _LC1_F14 & !_LC6_F14;

-- Node name is '|YIMA:4|:312' 
-- Equation name is '_LC6_F4', type is buried 
_LC6_F4  = LCELL( _EQ031);
  _EQ031 = !_LC5_F7 &  _LC5_F15
         #  _LC3_F12 & !_LC5_F7;

-- Node name is '|YIMA:4|~328~1' 
-- Equation name is '_LC6_F7', type is buried 
-- synthesized logic cell 
_LC6_F7  = LCELL( _EQ032);
  _EQ032 =  _LC3_F14
         #  _LC4_F7;

-- Node name is '|YIMA:4|~328~2' 
-- Equation name is '_LC7_F4', type is buried 
-- synthesized logic cell 
_LC7_F4  = LCELL( _EQ033);
  _EQ033 =  _LC3_F14
         #  _LC4_F7
         #  _LC2_F14
         #  _LC4_F4;

-- Node name is '|YIMA:4|~346~1' 
-- Equation name is '_LC5_F16', type is buried 
-- synthesized logic cell 
_LC5_F16 = LCELL( _EQ034);
  _EQ034 =  _LC2_F16
         #  _LC1_F16;

-- Node name is '|YIMA:4|:346' 
-- Equation name is '_LC1_F4', type is buried 
_LC1_F4  = LCELL( _EQ035);
  _EQ035 = !_LC3_F4 &  _LC6_F4
         # !_LC3_F4 &  _LC7_F4
         #  _LC5_F16;

-- Node name is '|YIMA:4|:361' 
-- Equation name is '_LC2_F15', type is buried 
_LC2_F15 = LCELL( _EQ036);
  _EQ036 =  _LC4_F15
         #  _LC6_F14;

-- Node name is '|YIMA:4|:367' 
-- Equation name is '_LC7_F8', type is buried 
_LC7_F8  = LCELL( _EQ037);
  _EQ037 =  _LC5_F9 &  _LC8_F7
         #  _LC2_F15 & !_LC4_F9;

-- Node name is '|YIMA:4|~379~1' 
-- Equation name is '_LC2_F7', type is buried 
-- synthesized logic cell 
_LC2_F7  = LCELL( _EQ038);
  _EQ038 =  _LC5_F7
         #  _LC2_F14;

-- Node name is '|YIMA:4|~379~2' 
-- Equation name is '_LC4_F8', type is buried 
-- synthesized logic cell 
_LC4_F8  = LCELL( _EQ039);
  _EQ039 =  _LC5_F9 &  _LC7_F7
         #  _LC5_F7
         #  _LC2_F14;

-- Node name is '|YIMA:4|:387' 
-- Equation name is '_LC2_F8', type is buried 
_LC2_F8  = LCELL( _EQ040);
  _EQ040 = !_LC3_F8 & !_LC4_F7 &  _LC7_F8
         # !_LC4_F7 &  _LC4_F8;

-- Node name is '|YIMA:4|~391~1' 
-- Equation name is '_LC8_F15', type is buried 
-- synthesized logic cell 
_LC8_F15 = LCELL( _EQ041);
  _EQ041 = !_LC2_F4
         #  _LC3_F14;

-- Node name is '|YIMA:4|:397' 
-- Equation name is '_LC3_F15', type is buried 
_LC3_F15 = LCELL( _EQ042);
  _EQ042 = !_LC1_F16 &  _LC2_F8
         # !_LC1_F16 &  _LC8_F15
         #  _LC2_F16;

-- Node name is '|YIMA:4|:420' 
-- Equation name is '_LC5_F8', type is buried 
_LC5_F8  = LCELL( _EQ043);
  _EQ043 =  _LC2_F15 & !_LC4_F9
         #  _LC1_F15 & !_LC4_F9;

-- Node name is '|YIMA:4|:430' 
-- Equation name is '_LC6_F8', type is buried 
_LC6_F8  = LCELL( _EQ044);
  _EQ044 =  _LC4_F8
         # !_LC3_F8 &  _LC5_F8
         # !_LC3_F8 &  _LC3_F9;

-- Node name is '|YIMA:4|:448' 
-- Equation name is '_LC8_F8', type is buried 
_LC8_F8  = LCELL( _EQ045);
  _EQ045 = !_LC6_F7 &  _LC6_F8
         #  _LC5_F16
         # !_LC2_F4;

-- Node name is '|YIMA:4|:457' 
-- Equation name is '_LC1_F15', type is buried 
_LC1_F15 = LCELL( _EQ046);
  _EQ046 =  _LC1_F14
         #  kin0 &  _LC5_F9 &  _LC7_F14;

-- Node name is '|YIMA:4|:471' 
-- Equation name is '_LC7_F12', type is buried 
_LC7_F12 = LCELL( _EQ047);
  _EQ047 =  _LC1_F15 & !_LC2_F15 & !_LC4_F9;

-- Node name is '|YIMA:4|~487~1' 
-- Equation name is '_LC1_F8', type is buried 
-- synthesized logic cell 
_LC1_F8  = LCELL( _EQ048);
  _EQ048 =  _LC5_F9 &  _LC7_F7
         #  _LC3_F8;

-- Node name is '|YIMA:4|~487~2' 
-- Equation name is '_LC8_F12', type is buried 
-- synthesized logic cell 
_LC8_F12 = LCELL( _EQ049);
  _EQ049 =  _LC1_F8
         #  _LC3_F9
         #  _LC6_F7
         #  _LC2_F7;

-- Node name is '|YIMA:4|:499' 
-- Equation name is '_LC5_F12', type is buried 
_LC5_F12 = LCELL( _EQ050);
  _EQ050 =  _LC2_F4 &  _LC7_F12
         #  _LC2_F4 &  _LC8_F12
         #  _LC5_F16;

-- Node name is '|YIMA:4|:511' 
-- Equation name is '_LC6_F15', type is buried 
_LC6_F15 = LCELL( _EQ051);
  _EQ051 =  kin0 &  _LC5_F9 &  _LC7_F14
         #  _LC4_F15;

-- Node name is '|YIMA:4|:525' 
-- Equation name is '_LC7_F15', type is buried 
_LC7_F15 = LCELL( _EQ052);
  _EQ052 = !_LC3_F9 & !_LC6_F14 &  _LC6_F15
         # !_LC3_F9 &  _LC4_F9;

-- Node name is '|YIMA:4|:537' 
-- Equation name is '_LC5_F4', type is buried 
_LC5_F4  = LCELL( _EQ053);
  _EQ053 = !_LC2_F14 &  _LC7_F15
         # !_LC2_F14 &  _LC5_F7
         #  _LC1_F8 & !_LC2_F14;

-- Node name is '|YIMA:4|:550' 
-- Equation name is '_LC8_F4', type is buried 
_LC8_F4  = LCELL( _EQ054);
  _EQ054 =  _LC2_F4 &  _LC6_F7
         #  _LC2_F4 &  _LC5_F4
         #  _LC5_F16;

-- Node name is '|YIMA:4|~577~1' 
-- Equation name is '_LC3_F12', type is buried 
-- synthesized logic cell 
_LC3_F12 = LCELL( _EQ055);
  _EQ055 =  _LC4_F9
         #  _LC1_F8
         #  _LC3_F9;

-- Node name is '|YIMA:4|:577' 
-- Equation name is '_LC4_F12', type is buried 
_LC4_F12 = LCELL( _EQ056);
  _EQ056 =  _LC3_F12
         #  _LC2_F15
         #  _LC1_F15;

-- Node name is '|YIMA:4|:586' 
-- Equation name is '_LC6_F12', type is buried 
_LC6_F12 = LCELL( _EQ057);
  _EQ057 = !_LC2_F7 &  _LC4_F12
         #  _LC4_F7;

-- Node name is '|YIMA:4|:601' 
-- Equation name is '_LC1_F12', type is buried 
_LC1_F12 = LCELL( _EQ058);
  _EQ058 =  _LC5_F16
         #  _LC2_F4 & !_LC3_F14 &  _LC6_F12;

-- Node name is '|YIMA:4|:640' 
-- Equation name is '_LC2_F12', type is buried 
_LC2_F12 = LCELL( _EQ059);
  _EQ059 =  _LC3_F14
         #  _LC2_F7 & !_LC4_F7
         # !_LC4_F7 &  _LC4_F12;

-- Node name is '|YIMA:4|~651~1' 
-- Equation name is '_LC2_F4', type is buried 
-- synthesized logic cell 
_LC2_F4  = LCELL( _EQ060);
  _EQ060 = !_LC3_F4 & !_LC4_F4;

-- Node name is '|YIMA:4|:654' 
-- Equation name is '_LC4_F16', type is buried 
_LC4_F16 = LCELL( _EQ061);
  _EQ061 =  _LC1_F16 & !_LC2_F16
         #  _LC2_F4 &  _LC2_F12 & !_LC2_F16;



Project Information                     e:\juzhenjianpan\jizhenjianpanyima.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 24,345K