📄 jizhenjianpanyima.rpt
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- 3 - F 16 DFFE + 0 2 0 5 |DCLK:30|a (|DCLK:30|:3)
- 6 - F 16 DFFE + 0 2 0 2 |DCLK:30|cnt1 (|DCLK:30|:4)
- 7 - F 16 DFFE + 0 2 0 2 |DCLK:30|cnt0 (|DCLK:30|:5)
- 2 - F 16 OR2 ! 2 2 0 3 |YIMA:4|:96
- 1 - F 16 AND2 2 2 0 3 |YIMA:4|:106
- 3 - F 04 OR2 ! 2 2 0 2 |YIMA:4|:116
- 1 - F 09 OR2 s ! 2 2 0 4 |YIMA:4|~126~1
- 4 - F 04 OR2 ! 2 2 0 2 |YIMA:4|:126
- 3 - F 14 AND2 0 4 0 5 |YIMA:4|:136
- 1 - F 07 AND2 s 0 2 0 4 |YIMA:4|~146~1
- 6 - F 09 AND2 s ! 3 1 0 2 |YIMA:4|~146~2
- 4 - F 07 OR2 ! 1 2 0 5 |YIMA:4|:146
- 2 - F 14 AND2 0 4 0 4 |YIMA:4|:156
- 5 - F 07 AND2 1 3 0 4 |YIMA:4|:166
- 7 - F 07 AND2 s 1 3 0 3 |YIMA:4|~186~1
- 3 - F 08 AND2 3 1 0 3 |YIMA:4|:186
- 3 - F 09 AND2 0 2 0 4 |YIMA:4|:196
- 8 - F 07 AND2 s 1 3 0 3 |YIMA:4|~206~1
- 4 - F 09 AND2 3 1 0 5 |YIMA:4|:206
- 6 - F 14 AND2 0 4 0 3 |YIMA:4|:216
- 4 - F 15 AND2 1 3 0 3 |YIMA:4|:226
- 3 - F 07 AND2 s 2 0 0 4 |YIMA:4|~236~1
- 1 - F 14 AND2 0 3 0 2 |YIMA:4|:236
- 2 - F 09 AND2 s 2 0 0 5 |YIMA:4|~246~1
- 5 - F 09 AND2 s 1 1 0 7 |YIMA:4|~246~2
- 5 - F 15 OR2 0 3 0 1 |YIMA:4|:282
- 6 - F 04 OR2 0 3 0 1 |YIMA:4|:312
- 6 - F 07 OR2 s 0 2 0 3 |YIMA:4|~328~1
- 7 - F 04 OR2 s 0 4 0 1 |YIMA:4|~328~2
- 5 - F 16 OR2 s 0 2 0 5 |YIMA:4|~346~1
- 1 - F 04 OR2 0 4 1 0 |YIMA:4|:346
- 2 - F 15 OR2 0 2 0 4 |YIMA:4|:361
- 7 - F 08 OR2 0 4 0 1 |YIMA:4|:367
- 2 - F 07 OR2 s 0 2 0 3 |YIMA:4|~379~1
- 4 - F 08 OR2 s 0 4 0 2 |YIMA:4|~379~2
- 2 - F 08 OR2 0 4 0 1 |YIMA:4|:387
- 8 - F 15 OR2 s 0 2 0 1 |YIMA:4|~391~1
- 3 - F 15 OR2 0 4 1 0 |YIMA:4|:397
- 5 - F 08 OR2 0 3 0 1 |YIMA:4|:420
- 6 - F 08 OR2 0 4 0 1 |YIMA:4|:430
- 8 - F 08 OR2 0 4 1 0 |YIMA:4|:448
- 1 - F 15 OR2 1 3 0 3 |YIMA:4|:457
- 7 - F 12 AND2 0 3 0 1 |YIMA:4|:471
- 1 - F 08 OR2 s 0 3 0 3 |YIMA:4|~487~1
- 8 - F 12 OR2 s 0 4 0 1 |YIMA:4|~487~2
- 5 - F 12 OR2 0 4 1 0 |YIMA:4|:499
- 6 - F 15 OR2 1 3 0 1 |YIMA:4|:511
- 7 - F 15 OR2 0 4 0 1 |YIMA:4|:525
- 5 - F 04 OR2 0 4 0 1 |YIMA:4|:537
- 8 - F 04 OR2 0 4 1 0 |YIMA:4|:550
- 3 - F 12 OR2 s 0 3 0 2 |YIMA:4|~577~1
- 4 - F 12 OR2 0 3 0 2 |YIMA:4|:577
- 6 - F 12 OR2 0 3 0 1 |YIMA:4|:586
- 1 - F 12 OR2 0 4 1 0 |YIMA:4|:601
- 2 - F 12 OR2 0 4 0 1 |YIMA:4|:640
- 2 - F 04 AND2 s 0 2 0 6 |YIMA:4|~651~1
- 4 - F 16 OR2 0 4 1 0 |YIMA:4|:654
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\juzhenjianpan\jizhenjianpanyima.rpt
jizhenjianpanyima
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 5/ 72( 6%) 0/ 72( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
E: 0/144( 0%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
F: 8/144( 5%) 32/ 72( 44%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\juzhenjianpan\jizhenjianpanyima.rpt
jizhenjianpanyima
** CLOCK SIGNALS **
Type Fan-out Name
DFF 6 |DCLK:30|a
INPUT 3 clk
Device-Specific Information: e:\juzhenjianpan\jizhenjianpanyima.rpt
jizhenjianpanyima
** EQUATIONS **
clk : INPUT;
kin0 : INPUT;
kin1 : INPUT;
kin2 : INPUT;
kin3 : INPUT;
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = _LC8_F16;
-- Node name is 'sel1'
-- Equation name is 'sel1', type is output
sel1 = _LC5_F14;
-- Node name is 'sel2'
-- Equation name is 'sel2', type is output
sel2 = _LC4_F14;
-- Node name is 'y0'
-- Equation name is 'y0', type is output
y0 = _LC4_F16;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC1_F12;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = _LC8_F4;
-- Node name is 'y3'
-- Equation name is 'y3', type is output
y3 = _LC5_F12;
-- Node name is 'y4'
-- Equation name is 'y4', type is output
y4 = _LC8_F8;
-- Node name is 'y5'
-- Equation name is 'y5', type is output
y5 = _LC3_F15;
-- Node name is 'y6'
-- Equation name is 'y6', type is output
y6 = _LC1_F4;
-- Node name is '|CNT:28|:7' = '|CNT:28|cn0'
-- Equation name is '_LC8_F16', type is buried
_LC8_F16 = DFFE(!_LC8_F16, _LC3_F16, VCC, VCC, VCC);
-- Node name is '|CNT:28|:6' = '|CNT:28|cn1'
-- Equation name is '_LC5_F14', type is buried
_LC5_F14 = DFFE( _EQ001, _LC3_F16, VCC, VCC, VCC);
_EQ001 = !_LC5_F14 & !_LC7_F14 & _LC8_F16
# _LC5_F14 & !_LC7_F14 & !_LC8_F16;
-- Node name is '|CNT:28|:5' = '|CNT:28|cn2'
-- Equation name is '_LC4_F14', type is buried
_LC4_F14 = DFFE( _EQ002, _LC3_F16, VCC, VCC, VCC);
_EQ002 = _LC4_F14 & !_LC7_F14 & !_LC8_F14
# !_LC4_F14 & !_LC7_F14 & _LC8_F14;
-- Node name is '|CNT:28|LPM_ADD_SUB:22|addcore:adder|:51' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_F14', type is buried
_LC8_F14 = LCELL( _EQ003);
_EQ003 = _LC5_F14 & _LC8_F16;
-- Node name is '|CNT:28|:15'
-- Equation name is '_LC7_F14', type is buried
!_LC7_F14 = _LC7_F14~NOT;
_LC7_F14~NOT = LCELL( _EQ004);
_EQ004 = !_LC4_F14
# !_LC8_F14;
-- Node name is '|DCLK:30|:3' = '|DCLK:30|a'
-- Equation name is '_LC3_F16', type is buried
_LC3_F16 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC3_F16 & _LC6_F16
# _LC3_F16 & _LC7_F16
# _LC6_F16 & _LC7_F16;
-- Node name is '|DCLK:30|:5' = '|DCLK:30|cnt0'
-- Equation name is '_LC7_F16', type is buried
_LC7_F16 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC3_F16 & _LC6_F16
# _LC6_F16 & !_LC7_F16
# !_LC3_F16 & !_LC7_F16;
-- Node name is '|DCLK:30|:4' = '|DCLK:30|cnt1'
-- Equation name is '_LC6_F16', type is buried
_LC6_F16 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC3_F16 & _LC6_F16
# !_LC3_F16 & _LC7_F16
# _LC6_F16 & _LC7_F16;
-- Node name is '|YIMA:4|:96'
-- Equation name is '_LC2_F16', type is buried
!_LC2_F16 = _LC2_F16~NOT;
_LC2_F16~NOT = LCELL( _EQ008);
_EQ008 = kin0
# !kin1
# !_LC1_F9
# _LC8_F16;
-- Node name is '|YIMA:4|:106'
-- Equation name is '_LC1_F16', type is buried
_LC1_F16 = LCELL( _EQ009);
_EQ009 = kin0 & !kin1 & _LC1_F9 & !_LC8_F16;
-- Node name is '|YIMA:4|:116'
-- Equation name is '_LC3_F4', type is buried
!_LC3_F4 = _LC3_F4~NOT;
_LC3_F4~NOT = LCELL( _EQ010);
_EQ010 = kin0
# !kin1
# !_LC1_F9
# !_LC8_F16;
-- Node name is '|YIMA:4|~126~1'
-- Equation name is '_LC1_F9', type is buried
-- synthesized logic cell
!_LC1_F9 = _LC1_F9~NOT;
_LC1_F9~NOT = LCELL( _EQ011);
_EQ011 = !kin3
# !kin2
# _LC4_F14
# _LC5_F14;
-- Node name is '|YIMA:4|:126'
-- Equation name is '_LC4_F4', type is buried
!_LC4_F4 = _LC4_F4~NOT;
_LC4_F4~NOT = LCELL( _EQ012);
_EQ012 = !kin0
# kin1
# !_LC1_F9
# !_LC8_F16;
-- Node name is '|YIMA:4|:136'
-- Equation name is '_LC3_F14', type is buried
_LC3_F14 = LCELL( _EQ013);
_EQ013 = _LC1_F7 & _LC2_F9 & _LC3_F7 & !_LC4_F14;
-- Node name is '|YIMA:4|~146~1'
-- Equation name is '_LC1_F7', type is buried
-- synthesized logic cell
_LC1_F7 = LCELL( _EQ014);
_EQ014 = _LC5_F14 & !_LC8_F16;
-- Node name is '|YIMA:4|~146~2'
-- Equation name is '_LC6_F9', type is buried
-- synthesized logic cell
!_LC6_F9 = _LC6_F9~NOT;
_LC6_F9~NOT = LCELL( _EQ015);
_EQ015 = kin1 & !kin2 & kin3 & !_LC4_F14;
-- Node name is '|YIMA:4|:146'
-- Equation name is '_LC4_F7', type is buried
!_LC4_F7 = _LC4_F7~NOT;
_LC4_F7~NOT = LCELL( _EQ016);
_EQ016 = _LC6_F9
# !kin0
# !_LC1_F7;
-- Node name is '|YIMA:4|:156'
-- Equation name is '_LC2_F14', type is buried
_LC2_F14 = LCELL( _EQ017);
_EQ017 = _LC2_F9 & _LC3_F7 & !_LC4_F14 & _LC8_F14;
-- Node name is '|YIMA:4|:166'
-- Equation name is '_LC5_F7', type is buried
_LC5_F7 = LCELL( _EQ018);
_EQ018 = kin0 & _LC5_F14 & !_LC6_F9 & _LC8_F16;
-- Node name is '|YIMA:4|~186~1'
-- Equation name is '_LC7_F7', type is buried
-- synthesized logic cell
_LC7_F7 = LCELL( _EQ019);
_EQ019 = kin0 & _LC4_F14 & !_LC5_F14 & !_LC8_F16;
-- Node name is '|YIMA:4|:186'
-- Equation name is '_LC3_F8', type is buried
_LC3_F8 = LCELL( _EQ020);
_EQ020 = kin1 & !kin2 & kin3 & _LC7_F7;
-- Node name is '|YIMA:4|:196'
-- Equation name is '_LC3_F9', type is buried
_LC3_F9 = LCELL( _EQ021);
_EQ021 = _LC5_F9 & _LC8_F7;
-- Node name is '|YIMA:4|~206~1'
-- Equation name is '_LC8_F7', type is buried
-- synthesized logic cell
_LC8_F7 = LCELL( _EQ022);
_EQ022 = kin0 & _LC4_F14 & !_LC5_F14 & _LC8_F16;
-- Node name is '|YIMA:4|:206'
-- Equation name is '_LC4_F9', type is buried
_LC4_F9 = LCELL( _EQ023);
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