📄 ywjcq.rpt
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! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\vhdl\shiyan\juzhenjianpan\ywjcq.rpt
ywjcq
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 15 DFFE + 1 1 1 1 :10
- 7 - A 15 DFFE + 1 1 1 1 :12
- 5 - A 15 DFFE + 1 1 1 1 :14
- 8 - A 15 DFFE + 1 1 1 1 :16
- 1 - A 15 DFFE + 1 1 1 1 :18
- 3 - A 15 DFFE + 1 1 1 1 :20
- 2 - A 15 DFFE + 1 1 1 1 :22
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\vhdl\shiyan\juzhenjianpan\ywjcq.rpt
ywjcq
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 0/ 48( 0%) 4/ 48( 8%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl\shiyan\juzhenjianpan\ywjcq.rpt
ywjcq
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 clk
Device-Specific Information: d:\vhdl\shiyan\juzhenjianpan\ywjcq.rpt
ywjcq
** EQUATIONS **
clk : INPUT;
load : INPUT;
y0 : INPUT;
y1 : INPUT;
y2 : INPUT;
y3 : INPUT;
y4 : INPUT;
y5 : INPUT;
y6 : INPUT;
-- Node name is 'dout0'
-- Equation name is 'dout0', type is output
dout0 = _LC2_A15;
-- Node name is 'dout1'
-- Equation name is 'dout1', type is output
dout1 = _LC3_A15;
-- Node name is 'dout2'
-- Equation name is 'dout2', type is output
dout2 = _LC1_A15;
-- Node name is 'dout3'
-- Equation name is 'dout3', type is output
dout3 = _LC8_A15;
-- Node name is 'dout4'
-- Equation name is 'dout4', type is output
dout4 = _LC5_A15;
-- Node name is 'dout5'
-- Equation name is 'dout5', type is output
dout5 = _LC7_A15;
-- Node name is 'dout6'
-- Equation name is 'dout6', type is output
dout6 = _LC4_A15;
-- Node name is ':10'
-- Equation name is '_LC4_A15', type is buried
_LC4_A15 = DFFE( _LC2_A15, GLOBAL( clk), !(GLOBAL( load) & !y6), !(GLOBAL( load) & y6), VCC);
-- Node name is ':12'
-- Equation name is '_LC7_A15', type is buried
_LC7_A15 = DFFE( _LC4_A15, GLOBAL( clk), !(GLOBAL( load) & !y5), !(GLOBAL( load) & y5), VCC);
-- Node name is ':14'
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = DFFE( _LC7_A15, GLOBAL( clk), !(GLOBAL( load) & !y4), !(GLOBAL( load) & y4), VCC);
-- Node name is ':16'
-- Equation name is '_LC8_A15', type is buried
_LC8_A15 = DFFE( _LC5_A15, GLOBAL( clk), !(GLOBAL( load) & !y3), !(GLOBAL( load) & y3), VCC);
-- Node name is ':18'
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = DFFE( _LC8_A15, GLOBAL( clk), !(GLOBAL( load) & !y2), !(GLOBAL( load) & y2), VCC);
-- Node name is ':20'
-- Equation name is '_LC3_A15', type is buried
_LC3_A15 = DFFE( _LC1_A15, GLOBAL( clk), !(GLOBAL( load) & !y1), !(GLOBAL( load) & y1), VCC);
-- Node name is ':22'
-- Equation name is '_LC2_A15', type is buried
_LC2_A15 = DFFE( _LC3_A15, GLOBAL( clk), !(GLOBAL( load) & !y0), !(GLOBAL( load) & y0), VCC);
Project Information d:\vhdl\shiyan\juzhenjianpan\ywjcq.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:08
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:09
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,756K
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