add.drc.rpt

vhdl 学习基础实例,有利于VHDL入门很有帮助

; Rule A110: Design should not contain asynchronous memory                                                                                                                                                                                                                                 ; On           ;    ;
; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source                                                                                                                                                                                 ; On           ;    ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                                                                                                                                    ; On           ;    ;
; Rule S103: More than one asynchronous signal port of the same register should not be driven by the same signal source                                                                                                                                                                    ; On           ;    ;
; Rule S104: Clock port and any other signal port of same register should not be driven by the same signal source                                                                                                                                                                          ; On           ;    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains                                                                                                                                                                                            ; On           ;    ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain                                                                                                                     ; On           ;    ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains                                                                                                                                                                                  ; On           ;    ;
; Rule H101: Only one VREF pin should be assigned to the HardCopy test pin in an I/O bank (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On           ;    ;
; Rule H102: PLL clock output drives multiple clock network types (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.)                         ; On           ;    ;
; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains                                                                                                                                                                            ; Off          ;    ;
; Rule M102: No reset signal defined to initialize the state machine                                                                                                                                                                                                                       ; Off          ;    ;
; Rule M103: State machine should not contain an unreachable state                                                                                                                                                                                                                         ; Off          ;    ;
; Rule M104: State machine should not contain a deadlock state                                                                                                                                                                                                                             ; Off          ;    ;
; Rule M105: State machine should not contain a dead transition                                                                                                                                                                                                                            ; Off          ;    ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+


+-------------------------------------------------------------------------------+
; Information only Violations                                                   ;
+----------------------------------------------------------+----------+---------+
; Rule name                                                ; Name     ; Fan-Out ;
+----------------------------------------------------------+----------+---------+
; Rule T102: Top nodes with the highest number of fan-outs ; Add0~307 ; 7       ;
; Rule T102: Top nodes with the highest number of fan-outs ; Add0~308 ; 7       ;
; Rule T102: Top nodes with the highest number of fan-outs ; Add0~311 ; 7       ;
; Rule T102: Top nodes with the highest number of fan-outs ; Add0~310 ; 7       ;
; Rule T102: Top nodes with the highest number of fan-outs ; b[0]     ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs ; a[0]     ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs ; a[2]     ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs ; b[1]     ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs ; a[1]     ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs ; Add0~309 ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs ; b[2]     ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs ; Mux4~3   ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; Mux6~3   ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; Mux5~3   ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; Mux3~3   ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; Mux2~3   ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; Mux1~3   ; 1       ;
; Rule T102: Top nodes with the highest number of fan-outs ; Mux0~3   ; 1       ;
+----------------------------------------------------------+----------+---------+


+---------------------------+
; Design Assistant Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Design Assistant
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Fri Apr 17 15:39:38 2009
Info: Command: quartus_drc --read_settings_files=on --write_settings_files=off add -c add
Info: (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 18 node(s) with highest fan-out.
    Info: Node "Add0~307" has 7 fan-out(s)
    Info: Node "Add0~308" has 7 fan-out(s)
    Info: Node "Add0~311" has 7 fan-out(s)
    Info: Node "Add0~310" has 7 fan-out(s)
    Info: Node "b[0]" has 3 fan-out(s)
    Info: Node "a[0]" has 3 fan-out(s)
    Info: Node "a[2]" has 2 fan-out(s)
    Info: Node "b[1]" has 2 fan-out(s)
    Info: Node "a[1]" has 2 fan-out(s)
    Info: Node "Add0~309" has 2 fan-out(s)
    Info: Node "b[2]" has 2 fan-out(s)
    Info: Node "Mux4~3" has 1 fan-out(s)
    Info: Node "Mux6~3" has 1 fan-out(s)
    Info: Node "Mux5~3" has 1 fan-out(s)
    Info: Node "Mux3~3" has 1 fan-out(s)
    Info: Node "Mux2~3" has 1 fan-out(s)
    Info: Node "Mux1~3" has 1 fan-out(s)
    Info: Node "Mux0~3" has 1 fan-out(s)
Info: Design Assistant information: finished post-fitting analysis of current design -- generated 18 information messages and 0 warning messages
Info: Quartus II Design Assistant was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 113 megabytes
    Info: Processing ended: Fri Apr 17 15:39:39 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01